74F1071

74F1071 FAIRCHILD | Alldatasheet

Document overview

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• PDF pages: 6

Technical content

Features

■ 18-bit array structure in 20-pin package ■ FAST  Bipolar voltage clamping action ■ Dual center pin grounds for min inductance ■ Robust design for ESD protection ■ Low input capacitance ■ Optimum voltage clamping for 5V CMOS/TTL

applications

Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Note: Simplified Component Representation FAST  is a registered trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74F1071SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

www.fairchildsemi.com 2 74F1071 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. Note 3: ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application.DC Electrical Characteristics Storage Temperature −65°C to +150°C Ambient Temperature under Bias −65°C to +125°C Junction Temperature under Bias −65°C to +150°C Input Voltage (Note 2) −0.5V to +6V Input Current (Note 2) −200 mA to +50 mA ESD (Note 3) Human Body Model (MIL-STD-883D method 3015.7) ±10 kV IEC 801-2 ±6 kV Machine Model (EIAJIC-121-1981) ±2 kV DC Latchup Source Current (JEDEC Method 17) ±500 mA Package Power Dissipation @+70°C Free Air Ambient Temperature 0 °C to +70°C Reverse Bias Voltage 0V to 5.25 V DC Thermal Resistance (θJA in Free Air) Symbol Parameter TA = +25°CT A = 0°C to +70°C Units Conditions Min Typ Max Min Max IIH Input HIGH Current 1.5 10 50 µA VIN = 5.25V; Untested Input @ GND 32 0 1 0 0 V IN = 5.5V; Untested Input @ GND V IZ = 1 mA; Untested Inputs @ GND 7.1 7.5 8.0 I Z = 50 mA; Untested Inputs @ GND V IF = −18 mA; Untested Inputs @ 5V ICT Adjacent Input Crosstalk 3 % C IN Input Capacitance 25 pF VBIAS = 0 VDC (small signal @ 1 MHz) 13 V BIAS = 5 VDC

3 www.fairchildsemi.com 74F1071 Typical Forward and Reverse V/I Characteristics Typical Reverse Conduction Characteristics Typical Forward Conduction Characteristics ESD Network CZ RZ Human Body Model 100 pF 1500 Ω IEC 801-2 150 pF 330 Ω Simulated ESD Voltage Clamping Test Circuit

www.fairchildsemi.com 4 74F1071 Unclamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Clamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Unclamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Clamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Typical Application 74F1071 ESD Protection of ASIC on User Port

5 www.fairchildsemi.com 74F1071 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

www.fairchildsemi.com 6 74F1071 18-Bit Undershoot/Overshoot Clamp Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com