SN74CB3T3384_15 TI1 | Alldatasheet
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/C0083/C0078/C0055/C0052/C0067/C0066/C0051/C0084/C0051/C0051/C0056/C0052 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0050/C0046/C0053/C0262/C0086/C0047/C0051/C0046/C0051/C0262/C0086 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0053/C0262/C0086/C0262/C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0084 /C0076/C0069/C0086/C0069/C0076 /C0083/C0072/C0073/C0070/C0084/C0069/C0082 SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Output Voltage Translation Tracks VCC /C0068Supports Mixed-Mode Signal Operation On All Data I/O Ports − 5-V Input Down To 3.3-V Output Level Shift With 3.3-V V CC − 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC /C00685-V-Tolerant I/Os With Device Powered-Up or Powered-Down /C0068Bidirectional Data Flow, With Near-Zero Propagation Delay /C0068Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical) /C0068Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical) /C0068Data and Control Inputs Provide Undershoot Clamp Diodes /C0068Low Power Consumption CC = 40 µA Max) /C0068VCC Operating Range From 2.3 V to 3.6 V /C0068Data I/Os Support 0 to 5-V Signaling Levels (For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) /C0068Control Inputs Can Be Driven by TTL or 5-V/3.3-V/2.5-V CMOS Outputs /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Latch-Up Performance Exceeds 250 mA Per JESD 17 /C0068ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) /C0068Supports Digital Applications: Level Translation, Memory Interleaving, Bus Isolation /C0068Ideal for Low-Power Portable Equipment DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND V CC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE description/ordering information
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − DW Tube SN74CB3T3384DW CB3T3384SOIC − DW Tape and reel SN74CB3T3384DWR CB3T3384 −40°C to 85°C SSOP (QSOP) − DBQ Tape and reel SN74CB3T3384DBQR CB3T3384 −40°C to 85°C TSSOP − PW Tube SN74CB3T3384PW KS384TSSOP − PW Tape and reel SN74CB3T3384PWR KS384 TVSOP − DGV Tape and reel SN74CB3T3384DGVR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). voltage (VOH ) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC-Voltage-Translation Characteristics is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
/C0083/C0078/C0055/C0052/C0067/C0066/C0051/C0084/C0051/C0051/C0056/C0052 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0050/C0046/C0053/C0262/C0086/C0047/C0051/C0046/C0051/C0262/C0086 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0053/C0262/C0086/C0262/C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0084 /C0076/C0069/C0086/C0069/C0076 /C0083/C0072/C0073/C0070/C0084/C0069/C0082 SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1A1 SW 1B1 1A5 1OE SW 1B5 2A1 SW 2B1 2A5 2OE SW 2B5 simplified schematic, each FET switch (SW) VG † A EN ‡ B † Gate Voltage (VG ) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. Control Circuit ‡ EN is the internal enable signal applied to the switch.
/C0083/C0078/C0055/C0052/C0067/C0066/C0051/C0084/C0051/C0051/C0056/C0052 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0050/C0046/C0053/C0262/C0086/C0047/C0051/C0046/C0051/C0262/C0086 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0053/C0262/C0086/C0262/C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0084 /C0076/C0069/C0086/C0069/C0076 /C0083/C0072/C0073/C0070/C0084/C0069/C0082 SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VIH High-level control input voltage VCC = 2.3 V to 2.7 V 1.7 5.5 VVIH High-level control input voltage VCC = 2.7 V to 3.6 V 2 5.5 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V 0 0.7 VVIL Low-level control input voltage VCC = 2.7 V to 3.6 V 0 0.8 V VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0055/C0052/C0067/C0066/C0051/C0084/C0051/C0051/C0056/C0052 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0050/C0046/C0053/C0262/C0086/C0047/C0051/C0046/C0051/C0262/C0086 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0053/C0262/C0086/C0262/C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0084 /C0076/C0069/C0086/C0069/C0076 /C0083/C0072/C0073/C0070/C0084/C0069/C0082 SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3 V, II = −18 mA −1.2 V VOH See Figures 3 and 4 IIN Control inputsVCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND ±10 µA VCC = 3.6 V, VI = VCC − 0.7 V to 5.5 V ±20 II VCC = 3.6 V, Switch ON, V = GND VI = 0.7 V to VCC − 0.7 V −40 µAII Switch ON, VIN = GND VI = 0 to 0.7 V ±5 µA IOZ ‡ VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC ±10 µA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA ICC VCC = 3.6 V, II/O = 0, VI = VCC or GND 40 AICC II/O = 0, Switch ON or OFF, VIN = VCC or GND VI = 5.5 V 40 µA ∆ICC § Control inputs VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 300 µA C in Control inputsVCC = 3.3 V, VIN = VCC or GND 3 pF C io(OFF) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC 5 pF C io(ON) VCC = 3.3 V, Switch ON, VI/O = 5.5 V or 3.3 V 4 pFC io(ON) CC Switch ON, VIN = GND VI/O = GND 12 pF VCC = 2.3 V, TYP at VCC = 2.5 V, IO = 24 mA 5 8 ron¶ CC TYP at VCC = 2.5 V, VI = 0 IO = 16 mA 5 8 Ωron¶ VCC = 3 V, IO = 64 mA 5 7 Ω VCC = 3 V, VI = 0 IO = 32 mA 5 7 VIN and IIN refer to control inputs. VI, VO , II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
/C0083/C0078/C0055/C0052/C0067/C0066/C0051/C0084/C0051/C0051/C0056/C0052 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0050/C0046/C0053/C0262/C0086/C0047/C0051/C0046/C0051/C0262/C0086 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0053/C0262/C0086/C0262/C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0084 /C0076/C0069/C0086/C0069/C0076 /C0083/C0072/C0073/C0070/C0084/C0069/C0082 SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNITPARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX UNIT tpd† A or B B or A 0.15 0.25 ns ten OE A or B 1 10.5 1 7.5 ns tdis OE A or B 1 6.5 1 8 ns † The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 2. Test Circuit and Voltage Waveforms
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 3. Data Output Voltage vs Data Input Voltage
Figure 4. VOH Values
www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 74CB3T3384DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CB3T3384 SN74CB3T3384DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CB3T3384 SN74CB3T3384DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T3384 SN74CB3T3384DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T3384 SN74CB3T3384PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 SN74CB3T3384PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 SN74CB3T3384PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 SN74CB3T3384PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 24-Apr-2015 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3T3384DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 SN74CB3T3384DWR SOIC DW 24 2000 367.0 367.0 45.0 SN74CB3T3384PWR TSSOP PW 24 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2
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