SN74CB3T3245_08 TI | Alldatasheet

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DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) NC GND V CC OE NC − No internal connection DESCRIPTION/ORDERING INFORMATION SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 V CC Operating Range From 2.3 V to 3.6 V Standard '245-Type Pinout Data I/Os Support to 5-V Signaling Levels (0.8 1.2 1.5 1.8 2.5 3.3 Output Voltage Translation Tracks V CC Control Inputs Can Be Driven by TTL or Supports Mixed-Mode Signal Operation on All 5-V/3.3-V CMOS Outputs Data I/O Ports I off Supports Partial-Power-Down Mode 5-V Input Down to 3.3-V Output Level Shift Operation With 3.3-V V CC Latch-Up Performance Exceeds 250 mA 5-V/3.3-V Input Down to 2.5-V Output Level Per JESD Shift With 2.5-V V CC ESD Performance Tested Per JESD 5-V-Tolerant I/Os With Device Powered Up or Powered Down 2000-V Human-Body Model (A114-B, Class II) Bidirectional Data Flow With Near-Zero Propagation Delay 1000-V Charged-Device Model (C101) Low ON-State Resistance on Characteristics Supports Digital Applications: Level on Ω Typ) Translation, PCI Interface, USB Interface, Memory Interleaving, Bus Isolation Low Input/Output Capacitance Minimizes Loading io(OFF) pF Typ) Ideal for Low-Power Portable Equipment Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption CC µ A Max) The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low ON-state resistance on allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks V CC The SN74CB3T3245 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 2003 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) VCC VCC 5.5 V 0 V NOTE A: If the input high-voltage (VIH) level is greater than or equal to (VCC − 1 V) and less than or equal to 5.5 V, then the output high-voltage (VOH) level will be equal to approximately the VCC voltage level. Input Voltages Output Voltages 0 V VCC − 1 V VCC − 1 V VCC IN OUT CB3T SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 Figure Typical DC Voltage Translation Characteristics The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable OE input and a standard '245 pinout. When OE is low, the 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the 8-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down I off The I off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74CB3T3245DW SOIC DW CB3T3245 Tape and reel SN74CB3T3245DWR SSOP (QSOP) DBQ Tape and reel SN74CB3T3245DBQR CB3T3245 C to C Tube SN74CB3T3245PW TSSOP PW KS245 Tape and reel SN74CB3T3245PWR TVSOP DGV Tape and reel SN74CB3T3245DGVR KS245 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUT INPUT/OUTPUT FUNCTION OE A L B A port B port H Z Disconnect

www.ti.com OE SW SW SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A EN(2) B Control Circuit VG(1) 1) Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > (VCC + VT). 2) EN is the internal enable signal applied to the switch. SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC)

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range (2) 0.5 V V IN Control input voltage range (2) (3) 0.5 V V I/O Switch I/O voltage range (2) (3) (4) 0.5 V I IK Control input clamp current V IN mA I I/OK I/O port clamp current V I/O mA I I/O ON-state switch current (5) 128 mA Continuous current through V CC or GND 100 mA DBQ package DGV package θ JA Package thermal impedance (6) C/W DW package PW package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) V I and V O are used to denote specific conditions for V I/O (5) I I and I O are used to denote specific conditions for I I/O (6) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 2.3 3.6 V V CC 2.3 V to 2.7 V 1.7 5.5 V IH High-level control input voltage V V CC 2.7 V to 3.6 V 5.5 V CC 2.3 V to 2.7 V 0.7 V IL Low-level control input voltage V V CC 2.7 V to 3.6 V 0.8 V I/O Data input/output voltage 5.5 V T A Operating free-air temperature C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com Electrical Characteristics (1) Switching Characteristics SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT V IK V CC I I mA 1.2 V V OH See Figure and Figure I IN Control inputs V CC 3.6 V IN 3.6 V to 5.5 V or GND µ A V I V CC 0.7 V to 5.5 V I I V CC 3.6 Switch ON, V IN V CC or GND V I 0.7 V to V CC 0.7 V µ A V I to 0.7 V I OZ (3) V CC 3.6 V O to 5.5 V I Switch OFF, V IN V CC or GND µ A I off V CC V O to 5.5 V I µ A V I V CC or GND V CC 3.6 I I/O I CC µ A Switch ON or OFF, V IN V CC or GND V I 5.5 V Δ I CC (4) Control inputs V CC V to 3.6 One input at V CC 0.6 Other inputs at V CC or GND 300 µ A C in Control inputs V CC 3.3 V IN V CC or GND pF C io(OFF) V CC 3.3 V I/O 5.5 3.3 or GND, Switch OFF, V IN V CC or GND pF V I/O 5.5 V or 3.3 V C io(ON) V CC 3.3 Switch ON, V IN V CC or GND pF V I/O GND I O mA 8.5 V CC 2.3 TYP at V CC 2.5 V I I O mA 8.5 r on (5) Ω I O mA V CC V I I O mA (1) V IN and I IN refer to control inputs. V I V O I I and I O refer to data pins. (2) All typical values are at V CC 3.3 V (unless otherwise noted), T A (3) For I/O ports, the parameter I OZ includes the input leakage current. (4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V CC or GND. (5) Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two or terminals. over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V V CC 3.3 V FROM TO 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX t pd (1) A or B B or A 0.15 0.25 ns t en OE A or B 10.5 ns t dis OE A or B 5.5 7.5 ns (1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL CL (see Note A) TEST CIRCUIT 2 × VCC Open GND RL RL tPLH tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + VΔ VOH − VΔ 0 V Output Control (VIN) VCC VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. 50 Ω VG1 VCC DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RLS1 VΔCL VCC VI tPHZ/tPZH tPLZ/tPZL tpd(s) Open Open 2 × VCC 2 × VCC Open Open 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω

3.6 V or GND

5.5 V or GND

3.6 V 5.5 V 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF 0.15 V 0.3 V 0.15 V 0.3 V Output Control (VIN) Input Generator Input Generator VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VO SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 Figure Test Circuit and Voltage Waveforms

www.ti.com TYPICAL CHARACTERISTICS V − Output Voltage − V OUTPUT VOLTAGE vs INPUT VOLTAGE O VI − Input Voltage − V OUTPUT VOLTAGE vs INPUT VOLTAGE VI − Input Voltage − V 0.0 1.0 2.0 3.0 4.0 0.0 1.0 2.0 3.0 4.0 VCC = 3 V IO = 1 µA TA = 25° C VCC = 2.3 V IO = 1 µA TA = 25° C V − Output Voltage − VO SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 Figure Data Output Voltage vs Data Input Voltage

www.ti.com TYPICAL CHARACTERISTICS 1.5 2.0 2.5 3.0 3.5 4.0 1.5 2.0 2.5 3.0 3.5 4.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VCC − Supply Voltage − V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 85° C OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VCC − Supply Voltage − V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 25° C OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VCC − Supply Voltage − V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = –40° C VOH − Output Voltage High − V VOH − Output Voltage High − V VOH − Output Voltage High − V 100 µA 8 mA 16 mA 24 mA 100 µA 8 mA 16 mA 24 mA 100 µA 8 mA 16 mA 24 mA 100 µA 8 mA 16 mA 24 mA SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER SCDS136 OCTOBER 2003 REVISED MARCH 2005 Figure V OH Values

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74CB3T3245DBQRE4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3245DBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3T3245DGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3T3245DGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DBQR ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CB3T3245DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3T3245PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Addendum-Page 1

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74CB3T3245DBQR SSOP/ QSOP PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3T3245DBQR SSOP/QSOP DBQ 20 2500 346.0 346.0 33.0 SN74CB3T3245DGVR TVSOP DGV 20 2000 346.0 346.0 29.0 SN74CB3T3245DWR SOIC DW 20 2000 346.0 346.0 41.0 SN74CB3T3245PWR TSSOP PW 20 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

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