SN74CB3Q3384A_1 TI | Alldatasheet
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DBQ, DGV, OR PW PACKAGE (TOP VIEW) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND V CC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE DESCRIPTION/ORDERING INFORMATION SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 Data and Control Inputs Provide Undershoot Clamp Diodes High-Bandwidth Data Path (up to 500 MHz (1) Low Power Consumption CC mA Typ) 5-V Tolerant I/Os With Device Powered Up or Powered Down V CC Operating Range From 2.3 V to 3.6 V Low and Flat ON-State Resistance Data I/Os Support to 5-V Signaling Levels on Characteristics Over Operating Range (0.8 1.2 1.5 1.8 2.5 3.3 on Ω Typ) Control Inputs Can Be Driven by TTL or Rail-to-Rail Switching on Data I/O Ports 5-V/3.3-V CMOS Outputs to 5-V Switching With 3.3-V V CC I off Supports Partial-Power-Down Mode Operation to 3.3-V Switching With 2.5-V V CC Latch-Up Performance Exceeds 100 mA Per Bidirectional Data Flow With Near-Zero JESD 78, Class II Propagation Delay ESD Performance Tested Per JESD Low Input/Output Capacitance Minimizes 2000-V Human-Body Model Loading and Signal Distortion (A114-B, Class II) io(OFF) pF Typ) 1000-V Charged-Device Model (C101) Fast Switching Frequency OE MHz Max) Supports Both Digital and Analog (1) For additional information regarding the performance Applications: PCI Interface, Differential Signal characteristics of the CB3Q family, refer to the TI application Interface, Memory Interleaving, Bus Isolation, report, CBT-C, CB3T, and CB3Q Signal-Switch Families literature number SCDA008. Low-Distortion Signal Gating ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING QSOP DBQ Tape and reel SN74CB3Q3384ADBQR CB3Q3384A Tube SN74CB3Q3384APW C to C TSSOP PW BU384A Tape and reel SN74CB3Q3384APWR TVSOP DGV Tape and reel SN74CB3Q3384ADGVR BU384A (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical
applications
sheet. PRODUCTION DATA information is current as of publication date. Copyright 2002 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) 1A1 SW 1B1 1A5 1OE SW 1B5 2A1 SW 2B1 2A5 2OE SW 2B5 SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 The SN74CB3Q3384A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance on The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3384A provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q3384A is organized as two 5-bit bus switches with separate output-enable OE OE inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down I off The I off circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (EACH 5-BIT BUS SWITCH) INPUT INPUT/OUTPUT FUNCTION OE A L B A port B port H Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC)
www.ti.com A EN(1) B (1) EN is the internal enable signal applied to the switch. Charge Pump VCC Absolute Maximum Ratings (1) Recommended Operating Conditions (1) SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 4.6 V V IN Control input voltage range (2) (3) 0.5 V V I/O Switch I/O voltage range (2) (3) (4) 0.5 V I IK Control input clamp current V IN mA I I/OK I/O port clamp current V I/O mA I I/O ON-state switch current (5) mA I O Continuous current through V CC or GND 100 mA DBQ package θ JA Package thermal impedance (6) DGV package C/W PW package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground, unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) V I and V O are used to denote specific conditions for V I/O (5) I I and I O are used to denote specific conditions for I I/O (6) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 2.3 3.6 V V CC 2.3 V to 2.7 V 1.7 5.5 V IH High-level control input voltage V V CC 2.7 V to 3.6 V 5.5 V CC 2.3 V to 2.7 V 0.7 V IL Low-level control input voltage V V CC 2.7 V to 3.6 V 0.8 V I/O Data input/output voltage 5.5 V T A Operating free-air temperature C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.
www.ti.com Electrical Characteristics (1) Switching Characteristics SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT V IK V CC 3.6 I I mA 1.8 V I IN Control inputs V CC 3.6 V IN to 5.5 V µ A V O to 5.5 Switch OFF, I OZ (3) V CC 3.6 µ A V I V IN V CC or GND I off V CC V O to 5.5 V I µ A I I/O I CC V CC 3.6 V IN V CC or GND mA Switch ON or OFF, Δ I CC (4) Control inputs V CC 3.6 One input at Other inputs at V CC or GND µ A V CC 3.6 A and B ports open, Per control mA/ I CCD (5) 0.15 0.25 input MHz Control input switching at 50% duty cycle C in Control inputs V CC 3.3 V IN 5.5 3.3 or 2.5 3.5 pF Switch OFF, C io(OFF) V CC 3.3 V I/O 5.5 3.3 or 3.5 pF V IN V CC or GND, Switch ON, C io(ON) V CC 3.3 V I/O 5.5 3.3 or pF V IN V CC or GND, V I I O mA V CC 2.3 TYP at V CC 2.5 V V I 1.7 I O mA 3.5 r on (6) Ω V I I O mA V CC V V I 2.4 I O mA 3.5 (1) V IN and I IN refer to control inputs. V I V O I I and I O refer to data pins. (2) All typical values are at V CC 3.3 V (unless otherwise noted), T A (3) For I/O ports, the parameter I OZ includes the input leakage current. (4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V CC or GND. (5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure (6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two or terminals. over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V V CC 3.3 V FROM TO 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX f OE (1) OE A or B MHz t pd (2) A or B B or A 0.09 0.15 ns t en OE A or B 1.5 7.2 1.5 ns t dis OE A or B 1.5 6.6 1.5 6.6 ns (1) Maximum switching frequency for control input O V CC V I R L M Ω C L (2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
www.ti.com VI - V TYPICAL ron vs VI VCC = 3.3 V TA = 25° C IO = -15 mA ron - ON-State Resistance - 0 2 4 6 8 10 12 14 16 18 20 OE Switching Frequency − MHz TYPICAL ICC vs OE SWITCHING FREQUENCY CCI − mA VCC = 3.3 V TA = 25° C A and B Ports Open One OE Switching SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 Figure Typical r on vs V I Figure Typical I CC vs OE Switching Frequency
www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL CL (see Note A) TEST CIRCUIT 2 × VCC Open GND RL RL tPLH tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + VΔ VOH − VΔ 0 V Output Control (VIN) VCC VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. 50 Ω VG1 VCC DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RLS1 VΔCL VCC VI tPHZ/tPZH tPLZ/tPZL tpd(s) Open Open 2 × VCC 2 × VCC GND GND 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω VCC or GND VCC or GND GND GND VCC VCC 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF 0.15 V 0.3 V 0.15 V 0.3 V Output Control (VIN) Input Generator Input Generator VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VO SN74CB3Q3384A 10-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS114D DECEMBER 2002 REVISED JUNE 2005 Figure Test Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74CB3Q3384ADBQRE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3Q3384ADBQRG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 74CB3Q3384ADGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q3384ADGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384ADBQR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CB3Q3384ADGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3384APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74CB3Q3384ADBQR SSOP/ QSOP PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3Q3384ADBQR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 SN74CB3Q3384ADGVR TVSOP DGV 24 2000 346.0 346.0 29.0 SN74CB3Q3384APWR TSSOP PW 24 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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