74CB3Q16245DGVRG4

SN74CB3Q16245 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 22

Technical content

www.ti.com

FEATURES

DGG, DGV, OR DL PACKAGE (TOP VIEW) NC 1B1 1B2 GND 1B3 1B4 V CC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 V CC 2B5 2B6 GND 2B7 2B8 NC 1OE 1A1 1A2 GND 1A3 1A4 V CC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V CC 2A5 2A6 GND 2A7 2A8 2OE NC - No internal connection SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 Member of the Texas Instruments Widebus Family High-Bandwidth Data Path (up to 500 MHz (1) 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance on Characteristics Over Operating Range on Ω Typ) Rail-to-Rail Switching on Data I/O Ports to 5-V Switching With 3.3-V V CC to 3.3-V Switching With 2.5-V V CC Bidirectional Data Flow With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion io(OFF) pF Typ) Fast Switching Frequency OE MHz Max) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption CC mA Typ) V CC Operating Range From 2.3 V to 3.6 V Data I/Os Support to 5-V Signaling Levels (0.8 1.2 1.5 1.8 2.5 3.3 Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs I off Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 2000-V Human-Body Model (A114-B, Class II) 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating (1) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families literature number SCDA008. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2004 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 The SN74CB3Q16245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance on The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16245 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q16245 is organized as two 8-bit bus switches with separate output-enable OE OE inputs. It can be used as two 8-bit bus switches, or as one 16-bit bus switch. When OE is low, the associated 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 8-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down I off The I off circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74CB3Q16245DL SSOP DL CB3Q16245 Tape and reel SN74CB3Q16245DLR C to C Tube SN74CB3Q16245DGG TSSOP DGG CB3Q16245 Tape and reel SN74CB3Q16245DGGR TVSOP DGV Tape and reel SN74CB3Q16245DGVR BW245 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH 8-BIT BUS SWITCH) INPUT INPUT/OUTPUT FUNCTION OE A L B A port B port H Z Disconnect

www.ti.com 1A1 SW 1B1 1A8 1OE SW 1B8 2A1 SW 2B1 2A8 2OE SW 2B8 A EN(1) B (1) EN is the internal enable signal applied to the switch. Charge Pump VCC SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 4.6 V V IN Control input voltage range (2) (3) 0.5 V V I/O Switch I/O voltage range (2) (3) (4) 0.5 V I IK Control input clamp current V IN mA I I/OK I/O port clamp current V I/O mA I I/O ON-state switch current (5) mA Continuous current through V CC or GND 100 mA DGG package θ JA Package thermal impedance (6) DGV package C/W DL package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground unless otherwise specified. (3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (4) V I and V O are used to denote specific conditions for V I/O (5) I I and I O are used to denote specific conditions for I I/O (6) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 2.3 3.6 V V CC 2.3 V to 2.7 V 1.7 5.5 V IH High-level control input voltage V V CC 2.7 V to 3.6 V 5.5 V CC 2.3 V to 2.7 V 0.7 V IL Low-level control input voltage V V CC 2.7 V to 3.6 V 0.8 V I/O Data input/output voltage 5.5 V T A Operating free-air temperature C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com Electrical Characteristics (1) Switching Characteristics SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT V IK V CC 3.6 I I mA 1.8 V I IN Control inputs V CC 3.6 V IN to 5.5 V µ A V O to 5.5 Switch OFF, I OZ (3) V CC 3.6 µ A V I V IN V CC or GND I off V CC V O to 5.5 V I µ A I I/O I CC V CC 3.6 V IN V CC or GND mA Switch ON or OFF, Δ I CC (4) Control inputs V CC 3.6 One input at Other inputs at V CC or GND µ A V CC 3.6 A and B ports open, Per control mA/ I CCD (5) 0.15 0.25 input MHz Control input switching at 50% duty cycle C in Control inputs V CC 3.3 V IN 5.5 3.3 or 3.5 pF Switch OFF, C io(OFF) V CC 3.3 V I/O 5.5 3.3 or pF V IN V CC or GND, Switch ON, C io(ON) V CC 3.3 V I/O 5.5 3.3 or pF V IN V CC or GND, V I I O mA V CC 2.3 TYP at V CC 2.5 V V I 1.7 I O mA r on (6) Ω V I I O mA V CC V V I 2.4 I O mA (1) V IN and I IN refer to control inputs. V I V O I I and I O refer to data pins. (2) All typical values are at V CC 3.3 V (unless otherwise noted), T A (3) For I/O ports, the parameter I OZ includes the input leakage current. (4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V CC or GND. (5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure (6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two or terminals. over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V V CC 3.3 V FROM TO 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX f OE (1) OE A or B MHz t pd (2) A or B B or A 0.18 0.3 ns t en OE A or B 1.5 1.5 ns t dis OE A or B ns (1) Maximum toggle frequency for OE control input O V CC V I R L M Ω C L (2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

www.ti.com ron− ON−State Resistance − VI − V Ω VCC = 3.3 V TA = 25° C IO = −15 mA 0 2 4 6 8 10 12 14 16 18 20 OE Switching Frequency − MHz CCI − mA VCC = 3.3 V TA = 25° C A and B ports Open One OE Switching SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 Figure Typical r on vs V I Figure Typical I CC vs OE Switching Frequency

www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL CL (see Note A) TEST CIRCUIT 2 × VCC Open GND RL RL tPLH tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + VΔ VOH − VΔ 0 V Output Control (VIN) VCC VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. 50 Ω VG1 VCC DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RLS1 VΔCL VCC VI tPHZ/tPZH tPLZ/tPZL tpd(s) Open Open 2 × VCC 2 × VCC GND GND 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω VCC or GND VCC or GND GND GND VCC VCC 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF 0.15 V 0.3 V 0.15 V 0.3 V Output Control (VIN) Input Generator Input Generator VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VO SN74CB3Q16245 16-BIT SWITCH 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH SCDS171A JULY 2004 REVISED MARCH 2005 Figure Test Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74CB3Q16245DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16245DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16245DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q16245DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16245DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16245DL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16245DLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q16245DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3Q16245DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74CB3Q16245DGVR TVSOP DGV 48 2000 346.0 346.0 33.0 SN74CB3Q16245DLR SSOP DL 48 1000 346.0 346.0 49.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 Pack Materials-Page 2

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SN74CB3Q16245DGGR Active Production TSSOP (DGG) | 48 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 SN74CB3Q16245DGGR.B Active Production TSSOP (DGG) | 48 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 SN74CB3Q16245DGVR Active Production TVSOP (DGV) | 48 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 BW245 SN74CB3Q16245DGVR.B Active Production TVSOP (DGV) | 48 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 BW245 SN74CB3Q16245DL Active Production SSOP (DL) | 48 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 SN74CB3Q16245DL.B Active Production SSOP (DL) | 48 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 SN74CB3Q16245DLR Active Production SSOP (DL) | 48 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 SN74CB3Q16245DLR.B Active Production SSOP (DL) | 48 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 CB3Q16245 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3Q16245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74CB3Q16245DGVR TVSOP DGV 48 2000 356.0 356.0 35.0 SN74CB3Q16245DLR SSOP DL 48 1000 367.0 367.0 55.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SN74CB3Q16245DL DL SSOP 48 25 473.7 14.24 5110 7.87 SN74CB3Q16245DL.B DL SSOP 48 25 473.7 14.24 5110 7.87 Pack Materials-Page 3

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

www.ti.com PACKAGE OUTLINE C 8.3

7.9 TYP

1.2 1.0 46X 0.5 48X 0.27 0.17 11.5 (0.15) TYP 0 - 8 0.15 0.05 0.25 GAGE PLANE 0.75 0.50 A 12.6 12.4 NOTE 3 B 6.2 6.0 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 1 48

0.08 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.350

www.ti.com EXAMPLE BOARD LAYOUT (7.5)

0.05 MAX

0.05 MIN

48X (1.5) 48X (0.3) 46X (0.5) (R0.05) TYP 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 24 25 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (7.5) 46X (0.5) 48X (0.3) 48X (1.5) (R0.05) TYP 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 24 25 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated