74C923

MM54C922 NSC | Alldatasheet

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Y 50 k X maximum switch on resistance Y On or off chip clock Y On-chip row pull-up devices Y 2 key roll-over Y Keybounce elimination with single capacitor Y Last key register at outputs Y TRI-STATE outpust LPTTL compatible Y Wide supply range 3V to 15V Y Low power consumption Connection Diagrams Pin Assignment for Dual-In-Line Package TL/F/6037–1 Top View Order Number MM54C922 or MM74C922 Pin Assignment for SOIC TL/F/6037–14 Top View Order Number MM74C922 Pin Assignment for DIP and SOIC Package TL/F/6037–2 Top View Order Number MM54C923 or MM74C923 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin V CC b 0.3V to V CC a 0.3V Operating Temperature Range MM54C922, MM54C923 b55§Ct o a125§C MM74C922, MM74C923 b40§Ct o a85§C Storage Temperature Range b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V VCC 18V Lead Temperature (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VTa Positive-Going Threshold Voltage V CC e 5V, I IN t 0.7 mA 3.0 3.6 4.3 V at Osc and KBM Inputs V CC e 10V, I IN t 1.4 mA 6.0 6.8 8.6 V VCC e 15V, I IN t 2.1 mA 9.0 10 12.9 V VTb Negative-Going Threshold Voltage V CC e 5V, I IN t 0.7 mA 0.7 1.4 2.0 V at Osc and KBM Inputs V CC e 10V, I IN t 1.4 mA 1.4 3.2 4.0 V VCC e 15V, I IN t 2.1 mA 2.1 5 6.0 V VIN(1) Logical ‘‘1’’ Input Voltage, V CC e 5V 3.5 4.5 V Except Osc and KBM Inputs V CC e 10V 8.0 9 V VCC e 15V 12.5 13.5 V VIN(0) Logical ‘‘0’’ Input Voltage, V CC e 5V 0.5 1.5 V Except Osc and KBM Inputs V CC e 10V 1 2 V VCC e 15V 1.5 2.5 V Irp Row Pull-Up Current at Y1, Y2, V CC e 5V, V IN e 0.1 V CC b2 b5 mA Y3, Y4 and Y5 Inputs V CC e 10V b10 b20 mA VCC e 15V b22 b45 mA VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA9 V VCC e 15V, I O eb 10 mA 13.5 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V, I O e 10 mA 0.5 V VCC e 10V, I O e 10 mA1 V VCC e 15V, I O e 10 mA 1.5 V Ron Column ‘‘ON’’ Resistance at V CC e 5V, V O e 0.5V 500 1400 X X1, X2, X3 and X4 Outputs V CC e 10V, V O e 1V 300 700 X VCC e 15V, V O e 1.5V 200 500 X ICC Supply Current V CC e 5V 0.55 1.1 mA Osc at 0V, (one Y low) V CC e 10V 1.1 1.9 mA VCC e 15V 1.7 2.6 mA IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mAat Output Enable IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mAat Output Enable CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage, 54C, V CC e 4.5V V CC b 1.5 V Except Osc and KBM Inputs 74C, V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage, 54C, V CC e 4.5V 0.8 V Except Osc and KBM Inputs 74C, V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, V CC e 4.5V 2.4 VIO eb 360 mA 74C, V CC e 4.75V 2.4 VIO eb 360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C, V CC e 4.5V 0.4 VIO eb 360 mA 74C, V CC e 4.75V 0.4 VIO eb 360 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

TL/F/6037–5 Truth Table Switch 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 Position Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 Y3,X4 Y4,X1 Y4,X2 Y4,X3 Y4,X4 Y5 *,X1 Y5 *,X2 Y5 *,X3 Y5 *,X4 D AA 0101010101010101 0 1 0 1 TB 0011001100110011 0 0 1 1 AC 0000111100001111 0 0 0 0 OD 0000000011111111 0 0 0 0 UE * 0000000000000000 1 1 1 1 T *Omit for MM54C922/MM74C922

Typical Performance Characteristics Typical I rp vs V IN at Any Y Input TL/F/6037–6 Typical R on vs V OUT at Any X Output TL/F/6037–7 Typical F SCAN vs C OSC TL/F/6037–8 Typical Debounce Period vs C KBM TL/F/6037–9 Typical Applications Synchronous Handshake (MM74C922) TL/F/6037–10 Synchronous Data Entry Onto Bus (MM74C922) TL/F/6037–11 Outputs are enabled when valid entry is made and go into TRI-STATE when key is released. Note 3: The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz.

Typical Applications (Continued) Asynchronous Data Entry Onto Bus (MM74C922) TL/F/6037–12 Outputs are in TRI-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to TRI-STATE. Expansion to 32 Key Encoder (MM74C922) TL/F/6037–13 Theory of Operation The MM74C922/MM74C923 Keyboard Encoders imple- ment all the logic necessary to interface a 16 or 20 SPST key switch matrix to a digital system. The encoder will con- vert a key switch closer to a 4(MM74C922) or 5(MM74C923) bit nibble. The designer can control both the keyboard scan rate and the key debounce period by altering the oscillator capacitor, C OSE, and the key bounce mask capacitor, C MSK. Thus, the MM74C922/MM74C923’s per- formance can be optimized for many keyboards. The keyboard encoders connect to a switch matrix that is 4 rows by 4 columns (MM74C922) or 5 rows by 4 columns (MM74C923). When no keys are depressed, the row inputs are pulled high by internal pull-ups and the column outputs sequentially output a logic ‘‘0’’. These outputs are open drain and are therefore low for 25% of the time and other- wise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2-bit counter, and a 2–4-bit decoder. When a key is depressed, key 0, for example, nothing will happen when the X1 input is off, since Y1 will remain high. When the X1 column is scanned, X1 goes low and Y1 will go low. This disables the counter and keeps X1 low. Y1 going low also initiates the key bounce circuit timing and locks out the other Y inputs. The key code to be output is a combina- tion of the frozen counter value and the decoded Y inputs. Once the key bounce circuit times out, the data is latched, and the Data Available (DAV) output goes high. If, during the key closure the switch bounces, Y1 input will go high again, restarting the scan and resetting the key bounce circuitry. The key may bounce several times, but as soon as the switch stays low for a debounce period, the closure is assumed valid and the data is latched. A key may also bounce when it is released. To ensure that the encoder does not recognize this bounce as another key closure, the debounce circuit must time out before another closure is recognized. The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key is depressed. Since all scanning has stopped, and all other Y inputs are disabled, the second key is not recognized until the first key is lifted and the key bounce circuitry has reset. The output latches feed TRI-STATE, which is enabled when the Output Enable (OE ) input is taken low.

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C922J or MM74C922J Ceramic Dual-In-Line Package (J) Order Number MM54C923J or MM74C923J

Physical Dimensions inches (millimeters) (Continued) Plastic Small Outline I.C. Package (M) Order Number MM74C922M or MM74C923M

Physical Dimensions inches (millimeters) (Continued) Plastic Dual-In-Line Package (N) Order Number MM54C922N or MM74C922N

MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder Physical Dimensions inches (millimeters) (Continued) Plastic Dual-In-Line Package (N) Order Number MM54C923N or MM74C923N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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