74C915

74C915 NSC | Alldatasheet

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o Semiconductor 3 g MM54C915/MM74C915 7-Segment-to-BCD Converter F General Description Sy The MM54C915/MM74C915 is a monolithic complementary The Minus output goes to a logical “1" whenever a minus | © MOS (CMOS) integrated circuit, constructed with N- and P- code is detected and is useful as a microprocessor inter- an channel enhancement-mode transistors. This circuit ac- rupt. The BCD outputs are in a flow-through condition when cepts 7-segment information and converts it into BCD infor- Latch Enable (LE) is at a logical “0” and latched when LE is mation. The true state of the Segment inputs can be select- at a logical “1”. The inputs will not clamp signals to the ‘ed by use of the Invert/Non-Invert control pin. A logical “0” —_positive supply, allowing simple level translation from MOS ‘on the Invert/Non-invert control pin selects active high true to TTL. decoding at the Segment inputs. A logical “1” on the Invert/ Non-Invert control pin selects active low true decoding at Features the Segment inputs. In addition to 4 TTL compatible BCD @ Wide supply range 3V-15V outputs, an Error output and Minus output are available. The High noise immunity 0.45 Vee (typ.) Error output goes to an active “1” whenever anon-standard +71 compatible fan out a TiL bead 7-segment code appears at the Segment input. The BCD vp ou outputs are forced into a TRI-STATE® condition when an Selectable active true inputs error is detected. This allows the user to program his own ™ TRI-STATE outputs ‘error code by tying the BCD outputs to Voc or Ground via On-chip latch high value resistors (~ 500k). The BCD outputs may alsobe @ Error output forced into TRI-STATE by a logical “1” on output enable == Minus output (OB), OR Logic Diagram . D> Poo wns samy 4 > [perLy ont . > [Petty ont 1> [Hed LX"? Suto~Do od] onne Turrso18-1 Connection Diagram Dual-in-Line Package SOMA UTS vent mus Order Number MM54C915* or MM74C915* *Piase lookinto Section 8, Append D for avalabity of varus package pes Coane Ce CCC CO CO ‘SEGMENT INPUTS or Tuvso10-2 Top View 6-147 - |

3| Absolute Maximum Ratings (note 1) MS If Military/Aerospace specified devices are required, ‘Storage Temperature Range —65°C to + 150°C =| contact the National Semiconductor Sales Office/ Power Dissipation = | _ Distributors for availability and specifications. Duak-In-Line 700 mw 2 Voltage at Any Output —0.3V to Voc + 0.3V ‘Small Outline 500 mW @ | Voltage at Any Input =0.3V to 18V Operating Voc Range 4.0V to 15V

2 Operating Temperature Range Maximum Voc 18V

= MM54C915 55°C to + 125°C Lead Temperature = MM74C915 —40°C to + 85°C (Soldering, 10 seconds) 260°C symbot_[ Parameter | Gonaitions [win typ [Max [Units CMOS TO CMOS Vinay Logical ‘1" Input Voltage: Voc = 5V v Voc = 10V v Voc = 15V v Vico) Logical “0” Input Voltage Voc = 5V v Voc = 10V v Voc = 15V Vv Vourit) Logical “1” Output Voltage lo = 10 pA Voc = 5V Vv Voc = 10V Vv Veco = 15V, v Vourio) Logical “0” Output Voltage lo = 10 pA Voc = 5V v Voc = 10V Vv Voc = 15V v lec ‘Supply Current Voc = 5V 0.25, mA Vec = 10V 075 mA Voc = 15V 1.00 mA (CMOS/TTL INTERFACE Vinca) Logical 1” Input Voltage MMs4C915, Vec = 4.5V Veo = 1.7 v MM740915 Voc = 4.75V Voc — 1.7 Vv Vino) Logical “0” Input Voltage MM54C915 Voc = 4.5V 08 v MM74C915 Voc = 4.75V 08 v Vourit) Logical 1" Output Voltage lo = —360 nA MMS54C915, Voc = 4.5V v MM74C915 Voc = 4.75V. v Vou) Logical “0” Output Voltage lo = 1.6 mA MMS54C915, Voc = 4.5V v MM74C915_ Voc = 4.75V v OUTPUT DRIVE (Short Circuit Current) lsource Output Source Current Ta = 25°C, Vo = OV P-Channel (Note 2) Voc = 5V -1.75 -33 mA i Voc = 10V ~8 ~15 mA Voo = 15V 15 -25 mA tink Output Sink Current Ta = 25°C, Vo = Veo N-Channet (Note 2) Voc = 5V 8 mA Voc = 10V 30 mA Voc = 15V. 50 mA 6-148 1 Be

Symbol_| Parameter | ———Gonaitions | win | tye [| max | unte | 3 tpao, teat Propagation Delay Time to C1 = 50 pF a Logical "0" or Logical “1"" Voe = 5V 500 1000 ns = Voc = 10V 300 600 ns = Voc = 15V 300 600 ns FS ton, tH Propagation Delay Time from RL = 10k, C, = 10pF se Logical “0” or Logical "1”" Voc = 5V 10 200 ns a into High Impedance State Voc = 10 75 130 ns Voc = 15 60 110 ns tho, tat Propagation Delay Time from RL = 10k, C, = 50 pF High Impedance State to a Voc = 5V 150 ns Logical “0” or Logical “1” Voc = 10V 80 ns Voc = 15V 70 ns ts Input Data Set-Up Time C, = 50 pF Voc = 5V 500 1000 ns Voc = 10V 300 600 ns Voc = 15V 300 600 ns tH Input Data Hold Time C= 50 pF Voc = 5V —150 ns Voc = 10V —100 ns Voc = 15V —100 ns On Arvin | | ss | 7s |r Sout TRISTATE OuputCapactance | AnyOutputwvoed | [10 |r “AC Paraalers a7 guerarood by OC corsatedtotng Note 1: “Abeoie Maxim Rings we hose values boyond whch he saey of tho doce cannot be guarantee, Except for “Operating Temperature Range” aaa esa tal he dovens shid be operate e tnove mes Te tbe of "lacneal Caractere” proves conations fo acta Jewoe couaion tote 2 These specications anh to ransent operon. tis not mano imply that he dvce shoud be operated a these lism sutaned operation Hate 3: Capactanc is quransed by pro testing. Truth Table | comurs_| [Soe [STs (s (3 bmi ian o olojoleo o ° 1 o}ojlo]r ° ° \\ ofolo{:| © | o 2 o}ojilo o ° 3 folo}i{x| o | o 4 olijolo ° ° Segment Identification S o}irj}oj}i ° ° . 6 o}ia}rfo ° o b ojifrfo ° ° th dy i folafata] o | o B |rtolojo{ o | o ih. g |rlojojr| o | o § rfolofi} o | o 7 1 1 1 , ° o ‘TLF/S918~-4 . x]xlxfxfor foo anomeinon |x| x] xix] 1 | 0 combinations | x |x] x|x{ ° 6 | X = represents TRISTATE condition TUF ISONO-3 6-149 an |

8 | Typical Applications = Multiplex 7-Segment to Straight BCD 8 [-—“secuenriromarion > iw um [sreaicnt aco > SEGMENT INFORMATION g LstPaaT INPUTS: OUTPUTS B WAMULTIPLEXED " = 7SEGMENT msacans = INFORMATION 10F Hn LATCH MINUS mutticexea [>] nase ERROR LW DIST sevect Tuisore-8 Memory Expansion from 7-Segment Outputs 6 anus isinant {SEGMENT INFORMATION SEG tanon WMULTIPLEXED ysaca1s SEGMENT INFORMATION 10F 0 Lato aco muctiecexen PPP] enasce aur eco inputs DATA INPUTS we ‘START a couNTER 20 x4 stor att ADDRESS Turiso1e-6 6-150