74C911

MM74C911 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

■ Direct segment drive (100 mA typ.) 3-STATE ■ 4 registers addressed like RAM ■ Internal oscillator and scanning circuit ■ Direct base drive to digit transistor ■ Segment expandability without external components ■ TTL compatible inputs ■ Power saver mode—5 µW (typ.) Ordering Code: Connection Diagram Pin Assignments for DIP Top View Order Number Package Number Package Description MM74C991N N28B 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS −010, 0.600” Wide

www.fairchildsemi.com 2 MM74C911 Truth Tables Input Control Output Control R = Refresh (digit lines sequentially pulsed) X = Don't Care Functional Description The MM74C911 display controller is manufactured on stan- dard metal gate CMOS technology. A single 5V 74 series TTL supply can be used for power and should be bypassed at the V CC pin to suppress current transients. The digit outputs directly drive the base of a grounded emitter digit transistor without the need of a Darlington con- figuration. If an MM74C911 is driving a digit transistor and also supplying digit information to a cascaded MM74C911, base resistors are needed in the digit transistors to provide an adequate high level to the digit inputs of the cascaded MM74C911. As seen in the Block Diagram, these display controllers contain four 8-bit registers; any one may be randomly writ- ten into. In normal operation, the internal multiplexer scans the registers and refreshes the display. In cascaded opera- tion, 1 MM74C911 serves as a master refresh device and cascaded MM74C911's are slaved to it through digit lines operating as inputs. The MM74C911 appears to a microprocessor as memory and to the user as a self-scan display. Since every seg- ment is under microprocessor control, great versatility is obtained. Low power standby operation occurs with both SOE and DIO inputs HIGH. This condition forces the MM74C911 to a quiescent state typically drawing less than 1 µA of supply current with a standby supply voltage as low as 3V. Logic Diagram Digit CE Address WE Operation K2 K1 0 0 0 0 Write Digit 1 0 0 0 1 Latch Digit 1 0 0 1 0 Write Digit 2 0 0 1 1 Latch Digit 2 0 1 0 0 Write Digit 3 0 1 0 1 Latch Digit 3 0 1 1 0 Write Digit 4 0 1 1 1 Latch Digit 4

1 X X X Disable Writing

DIO SOE Digit Lines Operation D4 D3 D2 D1 0 0 RRRR R e f r e s h D i s p l a y 0 1 RRRR D i s a b l e S e g m e n t O u t p u t s 1 0 0000 D i g i t s A r e N o w I n p u t s 1 0 0001 D i s p l a y D i g i t 1 1 0 0010 D i s p l a y D i g i t 2 1 0 0100 D i s p l a y D i g i t 3 1 0 1000 D i s p l a y D i g i t 4 1 1 0000 P o w e r S a v e r M o d e

3 www.fairchildsemi.com MM74C911 Absolute Maximum Ratings(Note 1) (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Range”, they are not meant to imply that the device should be operated at these lim- its. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All voltage reference to ground. Min/Max limits apply at −40°C ≤ TJ ≤ +85°C, unless otherwise noted Note 3: θJA measured in free-air with device soldered into printed circuit board. Voltage at Any Pin except Inputs −0.3V to VCC + 0.3V Voltage at Any Input except Digits −0.3V to +15V Operating Temperature Range, (TA) −40°C to +85°C Storage Temperature Range −65°C to +150°C Power Dissipation (PD ) Refer to P D(MAX) vs TA Graph Operating VCC Range 3V to 6V Absolute Maximum VCC 6.5V Lead Temperature (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units VIN(1) Logical “1” Input Voltage V CC = 5V 3.0 V VIN(0) Logical “0” Input Voltage 1.5 V IIN(1) Logical “1” Input Current V CC = 5V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 5V, VIN = 0V −1.0 −0.005 µA ICC Supply Current (Normal) V CC = 5V, Outputs Open 0.50 2.5 mA ICC Supply Current (Power Saver) VCC = 5V, SOE, DIO = “1”, 1 600 µA IOUT 3-ST ATE Output Current V O = 5V 0.03 10 µA VO = 0V −10 −0.03 CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 2V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V OUTPUT DRIVE ISH HIGH Level Segment Current V CC = 5V, VO = 3.4V TJ = 25°C −60 −100 mA TJ = 100°C −40 −60 mA IDH HIGH Level Digit Current V CC = 5V, VO = 3V TJ = 25°C −10 −20 mA TJ = 100°C −7 −10 mA VCC = 5V, VO = 1V TJ = 25°C −15 −40 mA TJ = 100°C −10 −15 mA VOUT(1) Logical “1” Output Voltage, V CC = 5V, IO = −360 µA4 . 6 V Any Digit VOUT(0) Logical “0” Output Voltage, V CC = 5V, IO = 360 µA0 . 4 V Any Output θJA Thermal Resistance (Note 3) 100 °C/W

www.fairchildsemi.com 4 MM74C911 VCC = 5V, tr = tf = 20 ns, CL = 50 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance guaranteed by periodic testing. Switching Time Waveforms Write Data Waveforms 3-STATE Waveforms Symbol Parameter Conditions Min Typ Max Units tCW Chip Enable to Write Enable Set-Up Time TJ = 25°C3 5 1 5 n s TJ = 125°C5 0 2 0 n s tAW Address to Write Enable Set-Up Time TJ = 25°C3 5 1 5 n s TJ = 125°C5 0 2 0 n s tWW Write Enable Width T J = 25°C 400 225 ns TJ = 125°C 450 250 ns tDW Data to Write Enable Set-Up Time T J = 25°C 390 225 ns TJ = 125°C 430 250 ns tWD Write Enable to Data Hold Time T J = 25°C0 −10 ns TJ = 125°C0 −15 ns tWA Write Enable to Address Hold Time T J = 25°C0 −10 ns TJ = 125°C0 −15 ns tWC Write Enable to Chip Enable Hold Time TJ = 25°C5 5 3 0 n s TJ = 125°C7 5 4 0 n s t1H , t0H Logical “1”, Logical “0” Levels into 3-STATE RL=10k, CL=10 pF TJ = 25°C 275 500 ns TJ = 125°C 325 600 ns tH1 , tH0 3-ST ATE to Logical “1” or R L=10k, CL=10 pF Logical “0” Levels T J = 25°C 325 600 ns TJ = 125°C 375 700 ns tD1 , tD0 Propagation Delay from Digit Input to TJ = 25°C 500 1000 ns Segment Output T J = 125°C 700 1400 ns tIB Interdigit Blanking Time T J = 25°C5 1 0 µs TJ = 125°C1 0 2 0 µs fMUX Multiplex Scan Frequency T J = 25°C5 2 5 H z TJ = 125°C3 7 5 H z C IN Input Capacitance (Note 5) 5 7.5 pF C OUT 3-ST ATE Output Capacitance (Note 5) 30 50 pF

5 www.fairchildsemi.com MM74C911 Switching Time Waveforms (Continued) Multiplexing Output Waveforms Read Data Waveforms Note A: All other digit lines are at a low level. DIO at a HIGH level. Typical Performance Characteristics Segment outputs if shorted to ground will exceed maximum power dissipation of the device. VCE is the saturation voltage of the digit drive transistor. Power Dissipation vs Temperature for Plastic Packages

Applications

Segment Output Structure Digit Output Structure

www.fairchildsemi.com 6 MM74C911 Input Protection Segment Expansion Typical Application *Base resistors may be necessary to limit base current.

7 www.fairchildsemi.com MM74C911 4-Digit, 16-Segment Alpha-Numeric Display Segment Identification

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C911 4-Digit Expandable Segment Display Controller LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Package Number N28B