Logic IC

74AXCH8T245RHLRG4

Texas Instruments

SN74AXCH8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Circuitry REVISED JANUARY 2019

Manufacturer: Texas Instruments

Document: 37 Pages / 978Kb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse 0-9 parts

Online Datasheet

Read 74AXCH8T245RHLRG4 online.

SN74AXCH8T245_V01 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 37

Technical content

1.5 V DIR1 DIR2VCCA VCCB Data Block GND GND 3.3 V Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AXCH8T245 SCES876A – AUGUST 2018– REVISED JANUARY 2019 SN74AXCH8T2458-BitDual-SupplyBusTransceiver withConfigurableVoltageTranslation,Tri-StateOutputs,andBus-HoldCircuitry

1 Features

1• Qualified Fully Configurable Dual-Rail Design Allows Each Port to Operate With a Power Supply Range From 0.65 V to 3.6 V

Operating Temperature From –40°C to +125°C
Bus-hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
Multiple Direction Control Pins to Allow Simultaneous Up and Down Translation
Up to 380 Mbps support when translating from 1.8 V to 3.3 V
VCC Isolation Feature to Effectively Isolate Both Buses in a Power-Down Scenario
Partial Power-Down Mode to Limit Backflow Current in a Power-Down Scenario
Compatible With SN74AVCH8T245 and 74AVCH8T245 Level Shifters
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 – 8000-V Human-Body Model – 1000-V Charged-Device Model

2 Applications

Enterprise and Communications
Wireless Infrastructure
Building Automation
Data Center Switches
Enterprise-Solid State Drive
Rack Server
EPOS

3 Description

The SN74AXCH8T245 device is an 8-bit non- inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, 3.3 V) and vice versa. The device operates by using two independent power-supply rails (VCCA and VCCB) . Data pins A1 through A8 are designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track VCCB, which accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXCH8T245 is compatible with a single- supply system. The SN74AXCH8T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable (OE) input is used to disable the outputs so the buses are effectively isolated. The SN74AXCH8T245 device is designed so the control pins (DIR and OE) are referenced to VCCA. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pull-up or pull- down resistors with the bus-hold circuitry is not recommended. If a supply is present for VCCA or VCCB, the bus-hold circuitry always remains active on all A and B ports respectively, independent of the direction control or output enable. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. The VCC isolation feature ensures that if either VCC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state. To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to VCCA through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AXCH8T245PW TSSOP (24) 7.80 mm × 4.40 mm SN74AXCH8T245RHL VQFN (24) 5.50 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic

12.2 Receiving Notification of Documentation Updates 25

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (August 2018) to Revision A Page

5 Pin Configuration and Functions

(1) PAD - may be grounded (recommended) or left floating. 24-Pin VQFN Top View Pin Functions PIN I/O DESCRIPTION NAME PW, RHL A1 3 I/O Input/output A1. Referenced to VCCA. A2 4 I/O Input/output A2. Referenced to VCCA. A3 5 I/O Input/output A3. Referenced to VCCA. A4 6 I/O Input/output A4. Referenced to VCCA. A5 7 I/O Input/output A5. Referenced to VCCA. A6 8 I/O Input/output A6. Referenced to VCCA. A7 9 I/O Input/output A7. Referenced to VCCA. A8 10 I/O Input/output A8. Referenced to VCCA. B1 21 I/O Input/output B1. Referenced to VCCB. B2 20 I/O Input/output B2. Referenced to VCCB. B3 19 I/O Input/output B3. Referenced to VCCB. B4 18 I/O Input/output B4. Referenced to VCCB. B5 17 I/O Input/output B5. Referenced to VCCB. B6 16 I/O Input/output B6. Referenced to VCCB. B7 15 I/O Input/output B7. Referenced to VCCB. B8 14 I/O Input/output B8. Referenced to VCCB. DIR1 2 I Direction-control signal. Referenced to VCCA. DIR2 11 I Direction-control signal. Referenced to VCCA. See Multiple Direction Control Pins for additional details. Tie to GND to maintain backwards compatibility with the SN74AVCH8T245 device. GND 12 — Ground 13 — Ground OE 22 I Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high- impedance mode. Referenced to VCCA. VCCA 1 — A-port supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V VCCB 23 — B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V 24 — B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCCA –0.5 4.2 V Supply voltage, VCCB –0.5 4.2 V Input voltage, VI(2) I/O ports (A port) –0.5 4.2 VI/O ports (B port) –0.5 4.2 Control inputs –0.5 4.2 Voltage applied to any output in the high-impedance or power-off state, VO(2) A port –0.5 4.2 V B port –0.5 4.2 Voltage applied to any output in the high or low state, VO(2) (3) A port –0.5 VCCA + 0.2 V B port –0.5 VCCB + 0.2 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Junction Temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)(2)(3) MIN MAX UNIT VCCA Supply voltage 0.65 3.6 V VCCB Supply voltage 0.65 3.6 V VIH High-level input voltage Data inputs VCCI = 0.65 V - 0.75 V VCCI × 0.70 V VCCI = 0.76 V - 1 V VCCI × 0.70 VCCI = 1.1 V - 1.95 V VCCI × 0.65 VCCI = 2.3 V - 2.7 V 1.6 VCCI = 3 V - 3.6 V 2 Control inputs (DIR, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA × 0.70 VCCA = 0.76 V - 1 V VCCA × 0.70 VCCA = 1.1 V - 1.95 V VCCA × 0.65 VCCA = 2.3 V - 2.7 V 1.6 VCCA = 3 V - 3.6 V 2 VIL Low-level input voltage Data inputs VCCI = 0.65 V - 0.75 V VCCI × 0.30 V VCCI = 0.76 V - 1 V VCCI × 0.30 VCCI = 1.1 V - 1.95 V VCCI × 0.35 VCCI = 2.3 V - 2.7 V 0.7 VCCI = 3 V - 3.6 V 0.8 Control inputs (DIR, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA × 0.30 VCCA = 0.76 V - 1 V VCCA × 0.30 VCCA = 1.1 V - 1.95 V VCCA × 0.35 VCCA = 2.3 V - 2.7 V 0.7 VCCA = 3 V - 3.6 V 0.8 VI Input voltage(3) 0 3.6 V VO Output voltage Active state 0 VCCO (2) V Tri-state 0 3.6 Δt/Δv Input transition rise or fall rate 10 ns/V TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) SN74AXCH8T245 UNITPW (TSSOP) RHL (VQFN)

24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 101.7 35 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.4 39.9 °C/W RθJB Junction-to-board thermal resistance 56.9 13.8 °C/W ψJT Junction-to-top characterization parameter 7.0 0.3 °C/W ψJB Junction-to-board characterization parameter 56.4 13.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1.4 °C/W

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated (1) VCCO is the VCC associated with the output port. (2) All typical values are for TA = 25°C. (3) The bus-hold circuit can sink at least the minimum low sustaining current at VIL(MAX). IBHL should be measured after lowering VI to GND and then raising it to VIL(MAX). (4) The bus-hold circuit can source at least the minimum high sustaining current at VIH(MIN). IBHH should be measured after raising VI to VCC and then lowering it to VIH(MIN). (5) An external driver must source at least IBHLO to switch this node from low to high.

6.5 Electrical Characteristics

Over recommended operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCCA VCCB –40°C to 85°C –40°C to 125°C UNIT MIN TYP(2) MAX MIN TYP(2) MAX VOH High-level output voltage VI = VIH V IOH = –50 µA 0.65 V 0.65 V 0.55 0.55 IOH = –200 µA 0.76 V 0.76 V 0.58 0.58 IOH = –500 µA 0.85 V 0.85 V 0.65 0.65 IOH = -3 mA 1.1 V 1.1 V 0.85 0.85 IOH = -6 mA 1.4 V 1.4 V 1.05 1.05 IOH = -8 mA 1.65 V 1.65 V 1.2 1.2 IOH = -9 mA 2.3 V 2.3 V 1.75 1.75 IOH = -12 mA 3 V 3 V 2.3 2.3 VOL Low-level output voltage VI = VIL V IOL = 50 µA 0.65 V 0.65 V 0.1 0.1 IOL = 200 µA 0.76 V 0.76 V 0.18 0.18 IOL = 500 µA 0.85 V 0.85 V 0.2 0.2 IOL = 3 mA 1.1 V 1.1 V 0.25 0.25 IOL = 6 mA 1.4 V 1.4 V 0.35 0.35 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 0.55 IOL = 12 mA 3 V 3 V 0.7 0.7 IBHL Bus-hold low sustaining current (3) VI= 0.20 V 0.65 V 0.65 V 4 4 µA VI= 0.23 V 0.76 V 0.76 V 8 7 VI= 0.26 V 0.85 V 0.85 V 10 10 VI= 0.39 V 1.1 V 1.1 V 20 20 VI= 0.49 V 1.4 V 1.4 V 40 30 VI= 0.58 V 1.65 V 1.65 V 55 45 VI= 0.7 V 2.3 V 2.3 V 90 80 VI= 0.8 V 3 V 3 V 145 135 IBHH Bus-hold high sustaining current (4) VI= 0.45 V 0.65 V 0.65 V –4 –4 µA VI= 0.53 V 0.76 V 0.76 V –8 –7 VI= 0.59 V 0.85 V 0.85 V –10 –10 VI= 0.71 V 1.1 V 1.1 V –20 –20 VI= 0.91 V 1.4 V 1.4 V –40 –30 VI= 1.07 V 1.65 V 1.65 V –55 –45 VI= 1.6 V 2.3 V 2.3 V –90 –80 VI= 2.0 V 3 V 3 V –145 –135 IBHLO Bus-hold low overdrive current (5) VI= 0 to VCC 0.75 V 0.75 V 40 40 µA 0.84 V 0.84 V 50 50 0.95 V 0.95 V 65 65 1.3 V 1.3 V 105 105 1.6 V 1.6 V 150 150 1.95 V 1.95 V 205 205 2.7 V 2.7 V 335 335 3.6V 3.6V 480 480

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) Over recommended operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCCA VCCB –40°C to 85°C –40°C to 125°C UNIT MIN TYP(2) MAX MIN TYP(2) MAX (6) An external driver must sink at least IBHHO to switch this node from high to low. IBHHO Bus-hold high overdrive current (6) VI= 0 to VCC 0.75 V 0.75 V –40 –40 µA 0.84 V 0.84 V –50 –50 0.95 V 0.95 V –65 –65 1.3 V 1.3 V –105 –105 1.6 V 1.6 V –150 –150 1.95 V 1.95 V –205 –205 2.7 V 2.7 V –335 –335 3.6V 3.6V –480 –480 II Input leakage current Control Inputs (DIR, OE): VI = VCCA or GND 0.65 V - 3.6 V 0.65 V - 3.6 V –0.5 0.5 –1 1 µA Ioff Partial power down current A Port: VI or VO = 0 V - 3.6 V 0 V 0 V - 3.6 V –8 8 –12 12 µA B Port: VI or VO = 0 V - 3.6 V 0 V - 3.6 V 0 V –8 8 –12 12 IOZ High- impedance state output current A Port: VO = VCCO or GND, VI = VCCI or GND, OE = VIH 3.6 V 3.6 V –8 8 –12 12 µA B Port: VO = VCCO or GND, VI = VCCI or GND, OE = VIH 3.6 V 3.6 V –8 8 –12 12 ICCA VCCA supply current VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 20 42 µA0 V 3.6 V –2 –12

3.6 V 0 V 13 27

current VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 20 40 µA0 V 3.6 V 13 27

3.6 V 0 V –2 –12

VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 30 60 µA Ci Input capacitance Control Inputs (DIR, OE): Cio Data I/O capacitance Ports A and B: OE = VCCA, VO = 1.65V DC +

1 MHz -16 dBm sine wave

3.3 V 3.3 V 7.3 7.3 pF

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 6.6 Switching Characteristics, VCCA = 0.7 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 178 0.5 115 0.5 83 0.5 49 ns –40°C to 125°C 0.5 178 0.5 115 0.5 83 0.5 49 B input to A output –40°C to 85°C 0.5 178 0.5 159 0.5 132 0.5 94 –40°C to 125°C 0.5 178 0.5 159 0.5 132 0.5 94 tdis Disable time OE input to A output –40°C to 85°C 0.5 194 0.5 194 0.5 194 0.5 194 ns –40°C to 125°C 0.5 194 0.5 194 0.5 194 0.5 194 OE input to B output –40°C to 85°C 0.5 216 0.5 179 0.5 158 0.5 78 –40°C to 125°C 0.5 216 0.5 179 0.5 158 0.5 78 ten Enable time OE input to A output –40°C to 85°C 0.5 240 0.5 240 0.5 240 0.5 240 ns –40°C to 125°C 0.5 240 0.5 240 0.5 240 0.5 240 OE input to B output –40°C to 85°C 0.5 292 0.5 180 0.5 125 0.5 76 –40°C to 125°C 0.5 292 0.5 180 0.5 125 0.5 76 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 47 0.5 50 0.5 62 0.5 151 ns –40°C to 125°C 0.5 47 0.5 50 0.5 62 0.5 151 B input to A output –40°C to 85°C 0.5 89 0.5 88 0.5 87 0.5 86 –40°C to 125°C 0.5 89 0.5 88 0.5 87 0.5 86 tdis Disable time OE input to A output –40°C to 85°C 0.5 194 0.5 194 0.5 194 0.5 194 ns –40°C to 125°C 0.5 194 0.5 194 0.5 194 0.5 194 OE input to B output –40°C to 85°C 0.5 70 0.5 69 0.5 67 0.5 101 –40°C to 125°C 0.5 70 0.5 69 0.5 67 0.5 101 ten Enable time OE input to A output –40°C to 85°C 0.5 240 0.5 240 0.5 240 0.5 240 ns –40°C to 125°C 0.5 240 0.5 240 0.5 240 0.5 240 OE input to B output –40°C to 85°C 0.5 69 0.5 69 0.5 84 0.5 552 –40°C to 125°C 0.5 69 0.5 69 0.5 84 0.5 552

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 6.7 Switching Characteristics, VCCA = 0.8 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 159 0.5 96 0.5 64 0.5 33 ns –40°C to 125°C 0.5 159 0.5 96 0.5 64 0.5 33 B input to A output –40°C to 85°C 0.5 117 0.5 97 0.5 79 0.5 54 –40°C to 125°C 0.5 117 0.5 97 0.5 79 0.5 54 tdis Disable time OE input to A output –40°C to 85°C 0.5 154 0.5 154 0.5 154 0.5 154 ns –40°C to 125°C 0.5 154 0.5 154 0.5 154 0.5 154 OE input to B output –40°C to 85°C 0.5 202 0.5 165 0.5 144 0.5 65 –40°C to 125°C 0.5 202 0.5 165 0.5 144 0.5 65 ten Enable time OE input to A output –40°C to 85°C 0.5 137 0.5 137 0.5 137 0.5 137 ns –40°C to 125°C 0.5 137 0.5 137 0.5 137 0.5 137 OE input to B output –40°C to 85°C 0.5 270 0.5 160 0.5 104 0.5 55 –40°C to 125°C 0.5 270 0.5 160 0.5 104 0.5 55 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 27 0.5 26 0.5 26 0.5 35 ns –40°C to 125°C 0.5 27 0.5 26 0.5 26 0.5 35 B input to A output –40°C to 85°C 0.5 44 0.5 43 0.5 42 0.5 41 –40°C to 125°C 0.5 44 0.5 43 0.5 42 0.5 41 tdis Disable time OE input to A output –40°C to 85°C 0.5 154 0.5 154 0.5 154 0.5 154 ns –40°C to 125°C 0.5 154 0.5 154 0.5 154 0.5 154 OE input to B output –40°C to 85°C 0.5 57 0.5 55 0.5 50 0.5 52 –40°C to 125°C 0.5 57 0.5 55 0.5 50 0.5 52 ten Enable time OE input to A output –40°C to 85°C 0.5 137 0.5 137 0.5 137 0.5 137 ns –40°C to 125°C 0.5 137 0.5 137 0.5 137 0.5 137 OE input to B output –40°C to 85°C 0.5 46 0.5 44 0.5 46 0.5 59 –40°C to 125°C 0.5 46 0.5 44 0.5 46 0.5 59

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 6.8 Switching Characteristics, VCCA = 0.9 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to output –40°C to 85°C 0.5 133 0.5 79 0.5 53 0.5 23 ns –40°C to 125°C 0.5 133 0.5 79 0.5 53 0.5 23 B input to A output –40°C to 85°C 0.5 84 0.5 64 0.5 53 0.5 41 –40°C to 125°C 0.5 84 0.5 64 0.5 53 0.5 41 tdis Disable time OE input to A output –40°C to 85°C 0.5 130 0.5 130 0.5 130 0.5 130 ns –40°C to 125°C 0.5 130 0.5 130 0.5 130 0.5 130 OE input to B output –40°C to 85°C 0.5 193 0.5 157 0.5 137 0.5 57 –40°C to 125°C 0.5 193 0.5 157 0.5 137 0.5 57 ten Enable time OE input to A output –40°C to 85°C 0.5 128 0.5 128 0.5 128 0.5 128 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 OE input to B output –40°C to 85°C 0.5 257 0.5 149 0.5 94 0.5 45 –40°C to 125°C 0.5 257 0.5 149 0.5 94 0.5 45 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 18 0.5 16 0.5 15 0.5 18 ns –40°C to 125°C 0.5 18 0.5 16 0.5 15 0.5 18 B input to A output –40°C to 85°C 0.5 29 0.5 25 0.5 23 0.5 22 –40°C to 125°C 0.5 29 0.5 25 0.5 23 0.5 22 tdis Disable time OE input to A output –40°C to 85°C 0.5 130 0.5 130 0.5 130 0.5 130 ns –40°C to 125°C 0.5 130 0.5 130 0.5 130 0.5 130 OE input to B output –40°C to 85°C 0.5 50 0.5 48 0.5 42 0.5 43 –40°C to 125°C 0.5 50 0.5 48 0.5 42 0.5 43 ten Enable time OE input to A output –40°C to 85°C 0.5 128 0.5 128 0.5 128 0.5 128 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 OE input to B output –40°C to 85°C 0.5 37 0.5 34 0.5 32 0.5 36 –40°C to 125°C 0.5 37 0.5 34 0.5 32 0.5 36

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 6.9 Switching Characteristics, VCCA = 1.2 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 95 0.5 54 0.5 40 0.5 15 ns –40°C to 125°C 0.5 95 0.5 54 0.5 40 0.5 15 B input to A output –40°C to 85°C 0.5 49 0.5 33 0.5 23 0.5 15 –40°C to 125°C 0.5 49 0.5 33 0.5 23 0.5 15 tdis Disable time OE input to A output –40°C to 85°C 0.5 47 0.5 47 0.5 47 0.5 47 ns –40°C to 125°C 0.5 47 0.5 47 0.5 47 0.5 47 OE input to B output –40°C to 85°C 0.5 181 0.5 147 0.5 127 0.5 49 –40°C to 125°C 0.5 181 0.5 147 0.5 127 0.5 49 ten Enable time OE input to A output –40°C to 85°C 0.5 40 0.5 40 0.5 40 0.5 40 ns –40°C to 125°C 0.5 40 0.5 40 0.5 40 0.5 40 OE input to B output –40°C to 85°C 0.5 221 0.5 132 0.5 81 0.5 34 –40°C to 125°C 0.5 221 0.5 132 0.5 81 0.5 34 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 11 0.5 9 0.5 8 0.5 8 ns –40°C to 125°C 0.5 11 0.5 9 0.5 8 0.5 8 B input to A output –40°C to 85°C 0.5 12 0.5 10 0.5 8 0.5 8 –40°C to 125°C 0.5 12 0.5 10 0.5 8 0.5 8 tdis Disable time OE input to A output –40°C to 85°C 0.5 47 0.5 47 0.5 47 0.5 47 ns –40°C to 125°C 0.5 47 0.5 47 0.5 47 0.5 47 OE input to B output –40°C to 85°C 0.5 42 0.5 40 0.5 34 0.5 34 –40°C to 125°C 0.5 42 0.5 40 0.5 34 0.5 34 ten Enable time OE input to A output –40°C to 85°C 0.5 39 0.5 40 0.5 40 0.5 40 ns –40°C to 125°C 0.5 39 0.5 40 0.5 40 0.5 40 OE input to B output –40°C to 85°C 0.5 25 0.5 22 0.5 20 0.5 19 –40°C to 125°C 0.5 25 0.5 22 0.5 20 0.5 19

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 6.10 Switching Characteristics, VCCA = 1.5 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 90 0.5 44 0.5 29 0.5 12 ns –40°C to 125°C 0.5 90 0.5 44 0.5 29 0.5 12 B input to A output –40°C to 85°C 0.5 47 0.5 27 0.5 18 0.5 11 –40°C to 125°C 0.5 47 0.5 27 0.5 18 0.5 11 tdis Disable time OE input to A output –40°C to 85°C 0.5 37 0.5 37 0.5 37 0.5 37 ns –40°C to 125°C 0.5 37 0.5 37 0.5 37 0.5 37 OE input to B output –40°C to 85°C 0.5 176 0.5 142 0.5 122 0.5 44 –40°C to 125°C 0.5 176 0.5 142 0.5 122 0.5 44 ten Enable time OE input to A output –40°C to 85°C 0.5 25 0.5 25 0.5 25 0.5 25 ns –40°C to 125°C 0.5 25 0.5 25 0.5 25 0.5 25 OE input to B output –40°C to 85°C 0.5 214 0.5 114 0.5 71 0.5 29 –40°C to 125°C 0.5 214 0.5 114 0.5 71 0.5 29 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 9 0.5 8 0.5 6 0.5 6 ns –40°C to 125°C 0.5 9 0.5 8 0.5 6 0.5 6 B input to A output –40°C to 85°C 0.5 9 0.5 8 0.5 6 0.5 5 –40°C to 125°C 0.5 9 0.5 8 0.5 6 0.5 5 tdis Disable time OE input to A output –40°C to 85°C 0.5 37 0.5 37 0.5 37 0.5 37 ns –40°C to 125°C 0.5 37 0.5 37 0.5 37 0.5 37 OE input to B output –40°C to 85°C 0.5 38 0.5 37 0.5 31 0.5 31 –40°C to 125°C 0.5 38 0.5 37 0.5 31 0.5 31 ten Enable time OE input to A output –40°C to 85°C 0.5 25 0.5 25 0.5 25 0.5 25 ns –40°C to 125°C 0.5 25 0.5 25 0.5 25 0.5 25 OE input to B output –40°C to 85°C 0.5 21 0.5 18 0.5 15 0.5 13 –40°C to 125°C 0.5 21 0.5 18 0.5 15 0.5 13

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 6.11 Switching Characteristics, VCCA = 1.8 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 88 0.5 43 0.5 25 0.5 10 ns –40°C to 125°C 0.5 88 0.5 43 0.5 25 0.5 10 B input to A output –40°C to 85°C 0.5 50 0.5 26 0.5 16 0.5 9 –40°C to 125°C 0.5 50 0.5 26 0.5 16 0.5 9 tdis Disable time OE input to A output –40°C to 85°C 0.5 35 0.5 35 0.5 35 0.5 35 ns –40°C to 125°C 0.5 35 0.5 35 0.5 35 0.5 35 OE input to B output –40°C to 85°C 0.5 174 0.5 139 0.5 119 0.5 42 –40°C to 125°C 0.5 174 0.5 139 0.5 119 0.5 42 ten Enable time OE input to A output –40°C to 85°C 0.5 20 0.5 20 0.5 20 0.5 20 ns –40°C to 125°C 0.5 20 0.5 20 0.5 20 0.5 20 OE input to B output –40°C to 85°C 0.5 213 0.5 111 0.5 67 0.5 27 –40°C to 125°C 0.5 213 0.5 111 0.5 67 0.5 27 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 8 0.5 7 0.5 6 0.5 5 ns –40°C to 125°C 0.5 8 0.5 7 0.5 6 0.5 5 B input to A output –40°C to 85°C 0.5 7 0.5 6 0.5 5 0.5 4 –40°C to 125°C 0.5 7 0.5 7 0.5 5 0.5 4 tdis Disable time OE input to A output –40°C to 85°C 0.5 35 0.5 35 0.5 35 0.5 35 ns –40°C to 125°C 0.5 35 0.5 35 0.5 35 0.5 35 OE input to B output –40°C to 85°C 0.5 36 0.5 35 0.5 30 0.5 29 –40°C to 125°C 0.5 36 0.5 35 0.5 30 0.5 29 ten Enable time OE input to A output –40°C to 85°C 0.5 20 0.5 20 0.5 20 0.5 20 ns –40°C to 125°C 0.5 20 0.5 20 0.5 20 0.5 20 OE input to B output –40°C to 85°C 0.5 19 0.5 16 0.5 13 0.5 11 –40°C to 125°C 0.5 19 0.5 16 0.5 13 0.5 11

SCES876A –AUGUST 2018– REVISED JANUARY 2019 www.ti.com Product Folder Links: SN74AXCH8T245 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 6.12 Switching Characteristics, VCCA = 2.5 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 87 0.5 42 0.5 23 0.5 8 ns –40°C to 125°C 0.5 87 0.5 42 0.5 23 0.5 8 B input to A output –40°C to 85°C 0.5 62 0.5 26 0.5 15 0.5 8 –40°C to 125°C 0.5 62 0.5 26 0.5 15 0.5 8 tdis Disable time OE input to A output –40°C to 85°C 0.5 28 0.5 28 0.5 28 0.5 28 ns –40°C to 125°C 0.5 28 0.5 28 0.5 28 0.5 28 OE input to B output –40°C to 85°C 0.5 173 0.5 137 0.5 117 0.5 40 –40°C to 125°C 0.5 173 0.5 137 0.5 117 0.5 40 ten Enable time OE input to A output –40°C to 85°C 0.5 13 0.5 13 0.5 13 0.5 13 ns –40°C to 125°C 0.5 13 0.5 13 0.5 13 0.5 13 OE input to B output –40°C to 85°C 0.5 211 0.5 107 0.5 63 0.5 24 –40°C to 125°C 0.5 211 0.5 107 0.5 63 0.5 24 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 6 0.5 6 0.5 5 0.5 5 ns –40°C to 125°C 0.5 6 0.5 6 0.5 5 0.5 5 B input to A output –40°C to 85°C 0.5 6 0.5 6 0.5 5 0.5 4 –40°C to 125°C 0.5 6 0.5 6 0.5 5 0.5 4 tdis Disable time OE input to A output –40°C to 85°C 0.5 28 0.5 28 0.5 28 0.5 28 ns –40°C to 125°C 0.5 28 0.5 28 0.5 28 0.5 28 OE input to B output –40°C to 85°C 0.5 34 0.5 33 0.5 28 0.5 28 –40°C to 125°C 0.5 34 0.5 33 0.5 28 0.5 28 ten Enable time OE input to A output –40°C to 85°C 0.5 13 0.5 13 0.5 13 0.5 13 ns –40°C to 125°C 0.5 13 0.5 13 0.5 13 0.5 13 OE input to B output –40°C to 85°C 0.5 16 0.5 14 0.5 10 0.5 9 –40°C to 125°C 0.5 16 0.5 14 0.5 10 0.5 9

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated 6.13 Switching Characteristics, VCCA = 3.3 V See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms. PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 87 0.5 41 0.5 22 0.5 8 ns –40°C to 125°C 0.5 87 0.5 41 0.5 22 0.5 8 B input to A output –40°C to 85°C 0.5 151 0.5 36 0.5 18 0.5 8 –40°C to 125°C 0.5 151 0.5 36 0.5 18 0.5 8 tdis Disable time OE input to A output –40°C to 85°C 0.5 27 0.5 27 0.5 27 0.5 27 ns –40°C to 125°C 0.5 27 0.5 27 0.5 27 0.5 27 OE input to B output –40°C to 85°C 0.5 172 0.5 136 0.5 116 0.5 39 –40°C to 125°C 0.5 172 0.5 136 0.5 116 0.5 39 ten Enable time OE input to A output –40°C to 85°C 0.5 11 0.5 11 0.5 11 0.5 11 ns –40°C to 125°C 0.5 11 0.5 11 0.5 11 0.5 11 OE input to B output –40°C to 85°C 0.5 210 0.5 106 0.5 62 0.5 23 –40°C to 125°C 0.5 210 0.5 106 0.5 62 0.5 23 PARAMETER TEST CONDITION B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A input to B output –40°C to 85°C 0.5 5 0.5 5 0.5 4 0.5 4 ns –40°C to 125°C 0.5 5 0.5 5 0.5 4 0.5 4 B input to A output –40°C to 85°C 0.5 6 0.5 5 0.5 5 0.5 4 –40°C to 125°C 0.5 6 0.5 5 0.5 5 0.5 4 tdis Disable time OE input to A output –40°C to 85°C 0.5 27 0.5 27 0.5 27 0.5 27 ns –40°C to 125°C 0.5 27 0.5 27 0.5 27 0.5 27 OE input to B output –40°C to 85°C 0.5 33 0.5 32 0.5 27 0.5 27 –40°C to 125°C 0.5 33 0.5 32 0.5 27 0.5 27 ten Enable time OE input to A output –40°C to 85°C 0.5 11 0.5 11 0.5 11 0.5 11 ns –40°C to 125°C 0.5 11 0.5 11 0.5 11 0.5 11 OE input to B output –40°C to 85°C 0.5 15 0.5 13 0.5 10 0.5 8 –40°C to 125°C 0.5 15 0.5 13 0.5 10 0.5 8

6.14 Operating Characteristics: TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CpdA Power dissipation capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 3.0 pF VCCA = VCCB = 0.8 V 3.0 VCCA = VCCB = 0.9 V 3.0 VCCA = VCCB = 1.2 V 3.1 VCCA = VCCB = 1.5 V 3.0 VCCA = VCCB = 1.8 V 3.2 VCCA = VCCB = 2.5 V 3.7 VCCA = VCCB = 3.3 V 4.4 CpdA Power dissipation capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 2.5 pF VCCA = VCCB = 0.8 V 2.5 VCCA = VCCB = 0.9 V 2.6 VCCA = VCCB = 1.2 V 2.6 VCCA = VCCB = 1.5 V 2.6 VCCA = VCCB = 1.8 V 2.7 VCCA = VCCB = 2.5 V 3.2 VCCA = VCCB = 3.3 V 3.9 CpdA Power dissipation capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 12.6 pF VCCA = VCCB = 0.8 V 12.3 VCCA = VCCB = 0.9 V 12.4 VCCA = VCCB = 1.2 V 12.4 VCCA = VCCB = 1.5 V 12.7 VCCA = VCCB = 1.8 V 13.6 VCCA = VCCB = 2.5 V 17.4 VCCA = VCCB = 3.3 V 20.9 CpdA Power dissipation capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.2 pF VCCA = VCCB = 0.8 V 1.1 VCCA = VCCB = 0.9 V 1.1 VCCA = VCCB = 1.2 V 1.0 VCCA = VCCB = 1.5 V 1.0 VCCA = VCCB = 1.8 V 0.9 VCCA = VCCB = 2.5 V 0.9 VCCA = VCCB = 3.3 V 0.9

www.ti.com SCES876A – AUGUST 2018– REVISED JANUARY 2019 Product Folder Links: SN74AXCH8T245 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Operating Characteristics: TA = 25°C (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CpdB Power dissipation capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 12.6 pF VCCA = VCCB = 0.8 V 12.4 VCCA = VCCB = 0.9 V 12.4 VCCA = VCCB = 1.2 V 12.4 VCCA = VCCB = 1.5 V 12.6 VCCA = VCCB = 1.8 V 13.6 VCCA = VCCB = 2.5 V 17.2 VCCA = VCCB = 3.3 V 20.8 CpdB Power dissipation capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.4 VCCA = VCCB = 0.8 V 1.3 pF VCCA = VCCB = 0.9 V 1.3 VCCA = VCCB = 1.2 V 1.2 VCCA = VCCB = 1.5 V 1.1 VCCA = VCCB = 1.8 V 1.1 VCCA = VCCB = 2.5 V 1.1 VCCA = VCCB = 3.3 V 1.0 CpdB Power dissipation capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 3.3 pF VCCA = VCCB = 0.8 V 3.3 VCCA = VCCB = 0.9 V 3.3 VCCA = VCCB = 1.2 V 3.2 VCCA = VCCB = 1.5 V 3.2 VCCA = VCCB = 1.8 V 3.3 VCCA = VCCB = 2.5 V 3.6 VCCA = VCCB = 3.3 V 4.4 CpdB Power dissipation capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 2.8 VCCA = VCCB = 0.8 V 2.8 pF VCCA = VCCB = 0.9 V 2.8 VCCA = VCCB = 1.2 V 2.8 VCCA = VCCB = 1.5 V 2.7 VCCA = VCCB = 1.8 V 2.8 VCCA = VCCB = 2.5 V 3.1 VCCA = VCCB = 3.3 V 3.9

2 X VCCO

7 Parameter Measurement Information

f =1 MHz
Z0 = 50 Ω
dv / dt ≤ 1 ns/V (1) CL includes probe and jig capacitance.

Figure 1. Load Circuit (1) Output waveform on the conditions that input is driven to a valid Logic Low. (2) Output waveform on the condition that input is driven to a valid Logic High. Figure 2. Load Circuit Conditions (1) VCCI is the supply pin associated with the input port. (2) VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 3. Propagation Delay

(1) Output waveform on the condition that input is driven to a valid Logic Low. (2) Output waveform on the condition that input is driven to a valid Logic High. (3) VCCO is the supply pin associated with the output port. (4) VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 4. Enable Time And Disable Time

8 Detailed Description

8.1 Overview

ranging from 0.65 V to 3.6 V.

8.2 Functional Block Diagram

Figure 5. Functional Block Diagram

(1) Input circuits of the data I/Os are always active and must be driven to a valid logic level.

8.3 Feature Description

8.3.2 Multiple Direction Control Pins

VCCA and VCCB are at least 1.40 V.

8.3.3 Bus-Hold Circuitry

recommended. See the Bus-Hold Circuit application note for more details. (SCLA015). pin is used to place all outputs into high impedance.

8.3.4 Ioff Supports Partial-Power-Down Mode Operation

8.4 Device Functional Modes

the possible modes of device operation based on the configuration of the control inputs. Table 1. Function Table(1)

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

translating a 0.7 V input to a 3.3 V output to interface between a system controller and a peripheral device.

9.2 Typical Application

Figure 6. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 2. Table 2. Design Parameters

9.2.2 Detailed Design Procedure

Input voltage range – Use the supply voltage of the device that is driving the SN74AXCH8T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
Output voltage range – Use the supply voltage of the device that the SN74AXCH8T245 device is driving to determine the output voltage range.

9.2.3 Application Curve

Figure 7. Translation Up (0.7 V to 3.3 V) at 2.5 MHz

10 Power Supply Recommendations

family of level translators, see the Power Sequencing for AXC Family of Devices application report.

11 Layout

11.1 Layout Guidelines

To assure reliability of the device, follow common printed-circuit board layout guidelines.

Use bypass capacitors on power supplies.
Use short trace lengths to avoid excessive loading.
Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements.

11.2 Layout Example

Figure 8. SN74AXCH8T245 Device Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: Texas Instruments, Implications of Slow or Floating CMOS Inputs application report Texas Instruments, Power Sequencing for AXC Family of Devices application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 74AXCH8T245RHLRG4 Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 74AXCH8T245RHLRG4.B Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245PWR Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245PWR.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245PWRG4 Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245PWRG4.B Active Production TSSOP (PW) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245RHLR Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AH8T245 SN74AXCH8T245RHLR.B Active Production VQFN (RHL) | 24 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 AH8T245 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 7-Oct-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AXCH8T245RHLRG4 VQFN RHL 24 3000 367.0 367.0 35.0 SN74AXCH8T245PWR TSSOP PW 24 2000 353.0 353.0 32.0 SN74AXCH8T245PWRG4 TSSOP PW 24 2000 353.0 353.0 32.0 SN74AXCH8T245RHLR VQFN RHL 24 3000 367.0 367.0 35.0 Pack Materials-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225250/B 12/2024 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RHL0024A AB PIN 1 INDEX AREA 3.6 3.4 5.6 5.4 0.08 C SEATING PLANE C1 MAX (0.1) TYP 0.05 0.00

0.1 C A B

0.05 C SYMM SYMM 1PIN 1 ID (OPTIONAL) 2.05±0.1 4.05±0.1 2X (0.55) 4.5 18X 0.5 12 13 2X 1.5 4X (0.2) 24X 0.30 0.18 24X 0.5 0.3

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225250/B 12/2024 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X SYMM SYMM 2X (1.5) 6X (0.67) (0.775) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (4.05) (2.05) (R0.05) TYP 2X (1.105) 2X (0.4) SOLDER MASK OPENING METAL UNDER SOLDER MASK 4X (0.2) 2X (0.55) (Ø 0.2) VIA TYP 1 24 12 13 4.6 4.4

0.07 MAX

(PREFERRED) METAL SOLDER MASK OPENING EXPOSED METAL

0.07 MIN

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225250/B 12/2024 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 18X SYMM SYMM 2X (1.5) (1.34) 6X (0.56) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (2.05) (R0.05) TYP 2X (0.84) METAL TYP 4X (0.2) 2X (0.55) 1 24 12 13 4.6 4.4 SOLDER MASK EDGE TYP

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

74AXCH8T245RHLRG4 specifications and overview.

Summary

SN74AXCH8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Circuitry REVISED JANUARY 2019

Description

SN74AXCH8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Circuitry REVISED JANUARY 2019

Source title 74AXCH8T245RHLRG4 Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer