74AVC2T45GT | DigiCamel IC Datasheet

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Technical content

General description The 74AVC2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V CC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between are referenced to V CC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The device is fully speciﬁed for partial power-down applications using IOFF . The IOFF circuitry disables the output, preventing any damaging backﬂow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. 2. Features n Wide supply voltage range: u VCC(A): 0.8 V to 3.6 V u VCC(B): 0.8 V to 3.6 V n High noise immunity n Complies with JEDEC standards: u JESD8-12 (0.8 V to 1.3 V) u JESD8-11 (0.9 V to 1.65 V) u JESD8-7 (1.2 V to 1.95 V) u JESD8-5 (1.8 V to 2.7 V) u JESD8-B (2.7 V to 3.6 V) n ESD protection: u HBM JESD22-A114E Class 3B exceeds 8000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Maximum data rates: u 500 Mbps (1.8 V to 3.3 V translation) u 320 Mbps (< 1.8 V to 3.3 V translation) u 320 Mbps (translate to 2.5 V or 1.8 V) u 280 Mbps (translate to 1.5 V) u 240 Mbps (translate to 1.2 V) n Suspend mode n Latch-up performance exceeds 100 mA per JESD 78 Class II 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 01 — 3 July 2007 Product data sheet

6.1 Pinning

6.2 Pin description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. Table 3. Pin description Table 4. Function table[1]

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. [1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] For VSSOP8 package: above 110°C the value of Ptot derates linearly with 8 mW/K. For XSON8 package: above 45°C the value of Ptot derates linearly with 2.4 mW/K.

Recommended operating conditions

[1] VCCO is the supply voltage associated with the output port. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 6. Recommended operating conditions

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. [1] VCCO is the supply voltage associated with the data output port. [2] VCCI is the supply voltage associated with the input port. must be held at VCCI or GND to ensure proper device operation.

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. [1] All typical values are measured at nominal VCC(A) and VCC(B). [2] tpd is the same as tPLH and tPHL . [3] tdis is the same as tPLZ and tPHZ . [4] ten is the same as tPZL and tPZH . [5] The enable time is a calculated value using the formula shown inSection 13.4 “Enable times”. [6] C PD is used to determine the dynamic power dissipation (PD inµW). L × VCC 2 × fo) = sum of the outputs. Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure7.

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. Measurement points are given inTable9. VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given inTable9. VOL and VOH are typical output voltage levels that occur with the output load. Table 9. Measurement points

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. [1] VCCI is the supply voltage associated with the data input port. [3] VCCO is the supply voltage associated with the output port. Test data is given inTable10. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance. VEXT = External voltage for measuring switching times. Table 10. Test data

13.1 Unidirectional logic level-shifting application

unidirectional logic level-shifting application. Table 11. Unidirectional logic level-shifting application

4 GND GND device GND

5 DIR DIR the GND (LOW level) determines B port to A port direction

13.2 Bidirectional logic level-shifting application

system-2 when changing directions. and then from system-2 to system-1. [1] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Z = high-impedance OFF-state. System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Table 12. Bidirectional logic level-shifting application[1][2]

1 H output input system-1 data to system-2

2 H Z Z system-2 is getting ready to send data to system-1. depends on the pull-up or pull-down. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on the pull-up or pull-down.

4 L input output system-2 data to system-1

13.3 Power-up considerations

13.4 Enable times

ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA)
ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVC2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the speciﬁed propagation delay.

Table 13. Typical total supply current (ICC(A) + ICC(B))

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 3 July 2007 24 of 28 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14. Package outline Fig 10. Package outline SOT765-1 (VSSOP8) UNIT A 1 A max. A 2 A 3 bp LH E Lp wyvce D (1) E(2) Z(1) q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.00 0.85 0.60 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.1 0°0.13 0.10.20.4 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.40 0.15 Q 0.21 0.19 SOT765-1 MO-187 02-06-07 w Mbp D Z e 0.12 8 5 q Q Lp (A3) detail X A L H E E c v M A X A y 2.5 5 mm0 scale VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 pin 1 index

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 3 July 2007 25 of 28 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Fig 11. Package outline SOT833-1 (XSON8) terminal 1 index area REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT833-1 04-07-22 04-11-09 DIMENSIONS (mm are the original dimensions) XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm D E e A 1 b LL1 e1 e1 0 1 2 mm scale Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. UNIT mm 0.25 0.17 2.0 1.9 0.35 0.27 A max b E 1.05 0.95 D ee 1 L 0.40 0.32 0.50.6 A (1) max 0.5 0.04 (2) (2) A

74AVC2T45_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 3 July 2007 27 of 28 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 July 2007 Document identifier: 74AVC2T45_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 19. Contents 13.1 Unidirectional logic level-shifting application. . 21 13.2 Bidirectional logic level-shifting application. . . 22

Product Information

74AVC2T45GT specifications and overview.

Summary

Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 01 - 3 July 2007

Description

Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 01 - 3 July 2007

Source title 74AVC2T45GT Datasheet(PDF) - NXP Semiconductors

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