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Technical content
- General description The 74AVC20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs (nOE), two direction inputs (nDIR) and dual supplies (VCC(A) and VCC(B)). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for bi-directional voltage level translation between any of the and nDIR are referenced to VCC(A), the 1Bn and 2Bn ports are referenced to VCC(B). A HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH impedance OFF-state. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all output ports will assume a high impedance OFF-state. 2. Features and benefits Wide supply voltage range: VCC(A): 0.8 V to 3.6 V VCC(B): 0.8 V to 3.6 V Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 2.5 V translation) 210 Mbit/s ( 1.1 V to 1.8 V translation) 74AVC20T245 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 7 — 8 March 2012 Product data sheet
Table 1. Ordering information
Product data sheet Rev. 7 — 8 March 2012 3 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state Pin numbers are shown for TSSOP56 packages only. Fig 2. Logic symbol 001aal239 1OE56 1 1DIR VCC(A) VCC(B) 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2OE29 28 2DIR VCC(A) VCC(B) 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10
Product data sheet Rev. 7 — 8 March 2012 4 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state 5. Pinning information
5.1 Pinning
Fig 3. Pin configuration SOT364-1 (TSSOP56) and SOT481-2 (TSSOP56) 74AVC20T245 1DIR 1OE 1B1 1A1 1B2 1A2 GND GND 1B3 1A3 1B4 1A4 VCC(B) VCC(A) 1B5 1A5 1B6 1A6 1B7 1A7 GND GND 1B8 1A8 1B9 1A9 1B10 1A10 2B1 2A1 2B2 2A2 2B3 2A3 GND GND 2B4 2A4 2B5 2A5 2B6 2A6 VCC(B) VCC(A) 2B7 2A7 2B8 2A8 GND GND 2B9 2A9 2B10 2A10 2DIR 2OE 001aal241
Product data sheet Rev. 7 — 8 March 2012 5 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state (1) This is not a supply pin. The substrat e is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SOT1134-2 (HXQFN60) 001aam129 74AVC20T245 D1 A32 A31 A30 A29 A28 A27 D4 B18 B19 B20A1 B8 B9 GND(1) B10 D7 D2 A11 A12 A13 A14 A15 A16 D8 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 B17 B16 B15 B14 B13 B12 B11 A10 terminal A1 index area
5.2 Pin description
[1] All GND pins must be connected to ground (0 V). [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] If at least one of V CC(A) or VCC(B) is at GND level, the device goes into suspend mode. [3] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). Table 2. Pin description Table 3. Function table [1]
[1] The minimum input and minimum output voltage ratings may be exceeded if the input and output clamping current ratings are ob served. [2] V CCO is the supply voltage associated with the output port. [3] V CCO + 0.5 V should not exceed 4.6 V. [4] Above 55 C the value of Ptot derates linearly with 8.0 mW/K. [5] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
- Recommended operating conditions
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the input port. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 5. Recommended operating conditions
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. Table 6. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Static characteristics …continued [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 8. Typical total supply current (I CC(A) + ICC(B))
[1] C PD is used to determine the dynamic power dissipation (PD in W). (CL VCC2 fo) = sum of the outputs. Table 9. Typical power dissi pation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V).
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 10. Typical dynamic characteristics at V CC(A) = 0.8 V and Tamb = 25 C [1] Table 11. Typical dynamic characteristics at V CC(B) = 0.8 V and Tamb = 25 C [1]
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
[1] V CCI is the supply voltage associated with the data input port. [2] V CCO is the supply voltage associated with the output port. Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Table 14. Measurement points
[1] V CCI is the supply voltage associated with the data input port. [3] V CCO is the supply voltage associated with the output port. Test data is given in Table 15. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Table 15. Test data
Product data sheet Rev. 7 — 8 March 2012 17 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics a. Propagation delay (nAn to nBn); V CC(A) = 0.8 V b. Propagation delay (nAn to nBn); V CC(B) = 0.8 V (1) V CC(B) = 0.8 V. (2) V CC(B) = 1.2 V. (3) V CC(B) = 1.5 V. (4) V CC(B) = 1.8 V. (5) V CC(B) = 2.5 V. (6) V CC(B) = 3.3 V. (1) V CC(A) = 0.8 V. (2) V CC(A) = 1.2 V. (3) V CC(A) = 1.5 V. (4) V CC(A) = 1.8 V. (5) V CC(A) = 2.5 V. (6) V CC(A) = 3.3 V. Fig 8. Typical propagation delay versus load capacitance; T amb = 25 C 001aai476 CL (pF) 06 0 4020 t pd (ns) (1) (2) (3) (4) (5) (6) CL (pF) 06 0 4020 001aai477 t pd (ns) (1) (2) (3) (4) (5) (6)
Product data sheet Rev. 7 — 8 March 2012 18 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai478 t PLH (ns) (1) (2) (3) (4) (5) CL (pF) 06 0 4020 001aai491 t PHL (ns) (4) (5) (1) (2) (3) CL (pF) 06 0 4020 001aai479 t PLH (ns) (1) (2) (3) (4) (5) CL (pF) 06 0 4020 001aai480 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 7 — 8 March 2012 19 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 10. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai481 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai482 t PHL (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai483 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai486 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 7 — 8 March 2012 20 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 11. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai485 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai484 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 7 — 8 March 2012 21 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state 13. Package outline Fig 12. Package outline SOT364-1 (TSSOP56) UNIT A1 A2 A3 bp cD (1) E(2) eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.2 0.1 o o0.1 DIMENSIONS (mm are the original dimensions). Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. SOT364-1 99-12-27 03-02-19 w M θ AA1 D Lp Q detail X E Z e c L X (A )3 0.25 12 8 56 29 y pin 1 index b H 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.10.080.250.8 0.4 p E v M A A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 A max. 1.2 0 2.5 5 mm scale MO-153
Product data sheet Rev. 7 — 8 March 2012 22 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state Fig 13. Package outline SOT481-2 (TSSOP56) UNIT A1 A2 A3 bp D (1) E (2) HE Lpce L Z (1)y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 1.05 0.80 0.23 0.13 0.20 0.09 11.4 11.2 4.5 4.3 6.6 6.20.4 8 o o0.07 0.080.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 0.25 0.4 0.1 w M bpe 12 8 56 29 Z pin 1 index θ A Lp detail X L (A )3 HE E c v M A X AD y 0 2.5 5 mm scale TSSOP56: plastic thin shrink small outline package; 56 leads; body width 4.4 mm SOT481-2 A max. 1.2
Product data sheet Rev. 7 — 8 March 2012 23 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state Fig 14. Package outline SOT1134-2 (HXQFN60) ReferencesOutline version European projection Issue date IEC JEDEC JEITA sot1134-2_po 11-08-15 Unit mm max nom min 0.50 0.08 0.05 0.02 0.28 0.23 0.18 1.95 1.85 1.75 6.1 6.0 5.9 3.95 3.85 3.75 1.0 2.5 4.5 0.195 0.145 0.095 0.1 A Dimensions HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4 x 6 x 0.5 mm SOT1134-2 A1 A2 0.42 0.40 0.38 bD 4.1 4.0 3.9 D h EE h 0.08 0.1 yy 1e 0.5 e1 e2 e3 3.0 e4 eT 0.49 eR 0.5 K 0.25 0.20 0.15 L 0.28 0.23 0.18 L 1 v 0.05 w 0 5 mm terminal 1 index area B AD E C yCy1 X detail X A A2 terminal 1 index area eTeR eT eR e4e3 e e 1/2 e 1/2 e A CBv Cw b A CBv Cw Dh K L Eh D5 D8 D6 D7 D1 D4 D2 D3 B20 B18 A27 A26 A17 B11 B17 A11 B8 B10 A16 A32 A10 eR eT eReT
Table 16. Abbreviations Table 17. Revision history
- For type number 74AVC20T245BX the sot code has changed to SOT1134-2. 74AVC20T245 v.6 20111207 Product data sheet - 74AVC20T245 v.5 Modifications:
- Legal pages updated. 74AVC20T245 v.5 20110616 Product data sheet - 74AVC20T245 v.4 74AVC20T245 v.4 20101124 Product data sheet - 74AVC20T245 v.3 74AVC20T245 v.3 20100622 Product data sheet - 74AVC20T245 v.2 74AVC20T245 v.2 20100318 Product data sheet - 74AVC20T245 v.1 74AVC20T245 v.1 20100111 Product data sheet - -
Product data sheet Rev. 7 — 8 March 2012 25 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state 16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 7 — 8 March 2012 26 of 27 NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AVC20T245 20-bit dual supply translating transceiver; 3-state © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 March 2012 Document identifier: 74AVC20T245 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 12 Typical propagation delay characteristics . . 17