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Technical content

General description The 74AVC1T45 is a single bit, dual supply transceiver with 3-state output that enables bidirectional level translation. It features one data input-output port (A and B), a direction control input (DIR) and dual supply pins (V CC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for 3.3 V). Pins A and DIR are referenced to V CC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to The device is fully speciﬁed for partial power-down applications using I OFF . The IOFF circuitry disables the output, preventing any damaging backﬂow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. 2. Features n Wide supply voltage range: u VCC(A): 0.8 V to 3.6 V u VCC(B): 0.8 V to 3.6 V n High noise immunity n Complies with JEDEC standards: u JESD8-12 (0.8 V to 1.3 V) u JESD8-11 (0.9 V to 1.65 V) u JESD8-7 (1.2 V to 1.95 V) u JESD8-5 (1.8 V to 2.7 V) u JESD8-B (2.7 V to 3.6 V) n ESD protection: u HBM JESD22-A114E Class 3B exceeds 8000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Maximum data rates: u 500 Mbit/s (1.8 V to 3.3 V translation) u 320 Mbit/s (< 1.8 V to 3.3 V translation) u 320 Mbit/s (translate to 2.5 V or 1.8 V) u 280 Mbit/s (translate to 1.5 V) u 240 Mbit/s (translate to 1.2 V) n Suspend mode n Latch-up performance exceeds 100 mA per JESD 78 Class II 74AVC1T45 Dual supply translating transceiver; 3-state Rev. 02 — 5 May 2009 Product data sheet

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. Table 1. Ordering information Table 2. Marking

6.1 Pinning

6.2 Pin description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [4] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. Table 3. Pin description Table 4. Function table[1]

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] For SC-88 packages: above 87.5°C the value of Ptotderates linearly with 4.0 mW/K. For XSON6 package: above 118°C the value of Ptotderates linearly with 7.8 mW/K.

Recommended operating conditions

[1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 6. Recommended operating conditions

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the data input port. At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] tpd is the same as tPLH and tPHL ; tdis is the same as tPLZ and tPHZ ; ten is the same as tPZL and tPZH . [1] tpd is the same as tPLH and tPHL ; tdis is the same as tPLZ and tPHZ ; ten is the same as tPZL and tPZH . [1] C PD is used to determine the dynamic power dissipation (PD inµW). L × VCC 2 × fo) = sum of the outputs. Table 8. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25°C [1] Table 9. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25°C [1] Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25°C [1][2] Voltages are referenced to GND (ground=0V ) .

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] tpd is the same as tPLH and tPHL ; tdis is the same as tPLZ and tPHZ ; ten is the same as tPZL and tPZH . Table 11. Dynamic characteristics for temperature range−40 °C to +85°C [1] Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure7; for wave forms seeFigure5 andFigure6.

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] tpd is the same as tPLH and tPHL ; tdis is the same as tPLZ and tPHZ ; ten is the same as tPZL and tPZH . Table 12. Dynamic characteristics for temperature range−40 °C to +125°C [1]

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. Measurement points are given inTable13. VOL and VOH are typical output voltage drops that occur with the output load. Measurement points are given inTable13. VOL and VOH are typical output voltage drops that occur with the output load. Table 13. Measurement points

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. [1] VCCI is the supply voltage associated with the data input port. [3] VCCO is the supply voltage associated with the output port. Test data is given inTable14. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance. VEXT = External voltage for measuring switching times. Table 14. Test data

13.1 Unidirectional logic level-shifting application

unidirectional logic level-shifting application. Table 15. Description unidirectional logic level-shifting application

2 GND GND device GND

3 A OUT output level depends on V

4 DIR DIR the GND (LOW level) determines B port to A port direction

5 B IN input threshold value depends on V

13.2 Bidirectional logic level-shifting application

and then from system-2 to system-1. Z = high-impedance OFF-state. Table 16. Description bidirectional logic level-shifting application[1]

1 H output input system-1 data to system-2

2 H Z Z system-2 is getting ready to send data to system-1. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold.

4 L input output system-2 data to system-1

13.3 Power-up considerations

13.4 Enable times

ten (DIR to A) = tdis (DIR to B) + tpd (B to A)
ten (DIR to B) = tdis (DIR to A) + tpd (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVC1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the speciﬁed propagation delay.

Table 17. Typical total supply current (ICC(A) + ICC(B))

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 17 of 21 NXP Semiconductors 74AVC1T45 Dual supply translating transceiver; 3-state 14. Package outline Fig 10. Package outline SOT363 (SC-88) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT363 SC-88 wB Mbp D e pin 1 index A Lp Q detail X H E E v M A AB y 0 1 2 mm scale c X 13 2 456 Plastic surface-mounted package; 6 leads SOT363 UNIT A 1 max bp cD E e1 H E Lp Qy wv mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.25 0.15 A 1.1 0.8 04-11-08 06-03-16

74AVC1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 18 of 21 NXP Semiconductors 74AVC1T45 Dual supply translating transceiver; 3-state Fig 11. Package outline SOT886 (XSON6) terminal 1 index area REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT886 MO-252 SOT886 04-07-15 04-07-22 DIMENSIONS (mm are the original dimensions) XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm D E e A 1 b LL1 0 1 2 mm scale Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. UNIT mm 0.25 0.17 1.5 1.4 0.35 0.27 A max b E 1.05 0.95 D ee 1 L 0.40 0.32 0.50.6 A (1) max 0.5 0.04 (2) (2) A

Conditions for ICC changed 74AVC1T45_1 20080118 Product data sheet - -

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control —This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AVC1T45 Dual supply translating transceiver; 3-state © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2009 Document identifier: 74AVC1T45_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 19. Contents 13.1 Unidirectional logic level-shifting application. . 14 13.2 Bidirectional logic level-shifting application. . . 15

Product Information

74AVC1T45 specifications and overview.

Summary

Dual supply translating transceiver; 3-state Rev. 02-5 May 2009

Description

Dual supply translating transceiver; 3-state Rev. 02-5 May 2009

Source title 74AVC1T45 Datasheet(PDF) - NXP Semiconductors

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