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Technical content
- General description The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: VCC(A): 0.8 V to 3.6 V VCC(B): 0.8 V to 3.6 V Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 74AVC16T245 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 3 — 9 June 2011 Product data sheet
Table 1. Ordering information
Product data sheet Rev. 3 — 9 June 2011 3 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Fig 2. Logic symbol 001aak425 1B1 1A1 1B2 1A2 1B3 1A3 1B4 1A4 1B5 1A5 1B6 1A6 1B7 1A7 1B8 1A8 1DIR 1OE VCC(B)VCC(A) 2B1 2A1 2B2 2A2 2B3 2A3 2B4 2A4 2B5 2A5 2B6 2A6 2B7 2A7 2B8 2A8 2DIR 2OE VCC(B)VCC(A)
Product data sheet Rev. 3 — 9 June 2011 4 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 5. Pinning information
5.1 Pinning
Fig 3. Pin configuration SOT362-1 and SOT480-1 (TSSOP48) Fig 4. Pin configuration SOT702-1 (VFBGA56) 74AVC16T245 1DIR 1OE 1B1 1A1 1B2 1A2 GND GND 1B3 1A3 1B4 1A4 VCC(B) VCC(A) 1B5 1A5 1B6 1A6 GND GND 1B7 1A7 1B8 1A8 2B1 2A1 2B2 2A2 GND GND 2B3 2A3 2B4 2A4 VCC(B) VCC(A) 2B5 2A5 2B6 2A6 GND GND 2B7 2A7 2B8 2A8 2DIR 2OE 001aak427 25 001aak428 74AVC16T245 Transparent top view K J H G F E C B A D 246135 ball A1 index area
Product data sheet Rev. 3 — 9 June 2011 5 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state (1) The die substrate is attached to this p ad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SOT1134-1 (HXQFN60U) D3A16A15A14A13A12A11D2 B9 B10 D7 A17 A18 B11 A19 B12 A20 B13 A21 B14 B8A10 D6 A22 B15 A23 B16 A24 B17 A25 A26D8 D4A27 B18 A28A29 B19B20 A30A31A32 74AVC16T245 001aak429 Transparent top view terminal 1 index area GND(1)
5.2 Pin description
[1] All GND pins must be connected to ground (0 V). [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. [2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B). [3] If at least one of V CC(A) or VCC(B) is at GND level, the device goes into suspend mode. Table 2. Pin description Table 3. Function table [1]
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] V CCO is the supply voltage associated with the output port. [3] V CCO + 0.5 V should not exceed 4.6 V. [4] Above 60 C the value of Ptot derates linearly with 5.5 mW/K. [5] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
- Recommended operating conditions
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the input port. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 5. Recommended operating conditions
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. Table 6. Typical static characteristics at Tamb = 25 C[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Static characteristics …continued [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
[1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 8. Typical total supply current (I CC(A) + ICC(B))
[1] C PD is used to determine the dynamic power dissipation (PD in W). (CL VCC2 fo) = sum of the outputs. Table 9. Typical power dissi pation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V).
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. [1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 10. Typical dynamic characteristics at V CC(A) = 0.8 V and Tamb = 25 C [1] Table 11. Typical dynamic characteristics at V CC(B) = 0.8 V and Tamb = 25 C [1]
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
[1] t pd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
[1] V CCI is the supply voltage associated with the data input port. [2] V CCO is the supply voltage associated with the output port. Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Table 14. Measurement points
[1] V CCI is the supply voltage associated with the data input port. [3] V CCO is the supply voltage associated with the output port. Test data is given in Table 15. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Table 15. Test data
Product data sheet Rev. 3 — 9 June 2011 17 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics a. Propagation delay (nAn to nBn); V CC(A) = 0.8 V b. Propagation delay (nAn to nBn); V CC(B) = 0.8 V (1) V CC(B) = 0.8 V. (2) V CC(B) = 1.2 V. (3) V CC(B) = 1.5 V. (4) V CC(B) = 1.8 V. (5) V CC(B) = 2.5 V. (6) V CC(B) = 3.3 V. (1) V CC(A) = 0.8 V. (2) V CC(A) = 1.2 V. (3) V CC(A) = 1.5 V. (4) V CC(A) = 1.8 V. (5) V CC(A) = 2.5 V. (6) V CC(A) = 3.3 V. Fig 9. Typical propagation delay versus load capacitance; T amb = 25 C 001aai476 CL (pF) 06 0 4020 t pd (ns) (1) (2) (3) (4) (5) (6) CL (pF) 06 0 4020 001aai477 t pd (ns) (1) (2) (3) (4) (5) (6)
Product data sheet Rev. 3 — 9 June 2011 18 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.2 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.2 V c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 10. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai478 t PLH (ns) (1) (2) (3) (4) (5) CL (pF) 06 0 4020 001aai491 t PHL (ns) (4) (5) (1) (2) (3) CL (pF) 06 0 4020 001aai479 t PLH (ns) (1) (2) (3) (4) (5) CL (pF) 06 0 4020 001aai480 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 3 — 9 June 2011 19 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 1.8 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 1.8 V c. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 2.5 V d. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 2.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 11. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai481 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai482 t PHL (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai483 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai486 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 3 — 9 June 2011 20 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state a. LOW to HIGH propagation delay (nAn to nBn); VCC(A) = 3.3 V b. HIGH to LOW propagation delay (nAn to nBn); VCC(A) = 3.3 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Fig 12. Typical propagation delay versus load capacitance; T amb = 25 C CL (pF) 06 0 4020 001aai485 t PLH (ns) (1) (2) (3) (5) (4) CL (pF) 06 0 4020 001aai484 t PHL (ns) (1) (2) (3) (5) (4)
Product data sheet Rev. 3 — 9 June 2011 21 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 13. Package outline Fig 13. Package outline SOT362-1 (TSSOP48) UNIT A1 A2 A3 bp cD (1) E(2) eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.2 0.1 o o0.1 DIMENSIONS (mm are the original dimensions). Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. SOT362-1 99-12-27 03-02-19 w M θ AA1 D Lp Q detail X E Z e c L X (A )3 0.25 12 4 48 25 y pin 1 index b H 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.258.3 7.9 0.50 0.35 0.8 0.40.080.8 0.4 p E v M A A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 A max. 1.2 0 2.5 5 mm scale MO-153
Product data sheet Rev. 3 — 9 June 2011 22 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Fig 14. Package outline SOT480-1 (TSSOP48) UNIT A1 A2 A3 bp D (1) E (2) HE Lpce L Q Z (1)y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 IEC JEDEC JEITA mm 0.15 0.05 0.95 0.85 0.23 0.13 0.20 0.09 9.8 9.6 4.5 4.3 6.6 6.20.4 0.4 0.3 o o0.07 0.080.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.7 0.5 SOT480-1 MO-153 0.25 0.4 0.1 w M bpe 12 4 48 25 Z pin 1 index θ A Lp Q detail X L (A )3 HE E c v M A X AD y 0 2.5 5 mm scale TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 A max. 1.1
Product data sheet Rev. 3 — 9 June 2011 23 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Fig 15. Package outline SOT702-1 (VFBGA56) 0.65 A1 b A2UNIT D ye REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 IEC JEDEC JEITA mm 1 0.3 0.2 0.7 0.6 4.6 4.4 7.1 6.9 0.45 0.35 0.08 0.1 3.25 5.85 DIMENSIONS (mm are the original dimensions) SOT702-1 MO-225 E 0.15 v 0.08 w 0 2.5 5 mm scale SOT702-1VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm A max. A detail X yy1 C e e b X D E C A B C D E F H G J K 246135 ball A1 index area B A 1/2 e 1/2 e A C C B∅ v M ∅ w M ball A1 index area
Product data sheet Rev. 3 — 9 June 2011 24 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Fig 16. Package outline SOT1134-1 (HXQFN60U) ReferencesOutline version European projection Issue date IEC JEDEC JEITA sot1134-1_po 08-12-17 09-01-22 Unit mm max nom min 0.50 0.48 0.46 0.05 0.02 0.00 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 1 2.5 4.5 0.125 0.075 0.025 0.07 A Dimensions HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm SOT1134-1 A1 b 0.35 0.30 0.25 DD h EE h 0.08 0.1 yy 1e 0.5 e1 e2 e3 e4 eR 0.5 k 0.25 0.20 0.15 L 0.35 0.30 0.25 L 1 v 0.05 w 0 2.5 5 mm scale A CBv Cw B A terminal 1 index area D E C yCy1 X detail X A A1 eR e3 e4 e e 1/2 e 1/2 e b A CBv Cw k L B20 B18 A27 D4A32 D7D6 D3D2 Dh Eh terminal 1 index area A11 A16 B10B8 A17 B11 B17 A26A1 A10
Table 16. Abbreviations Table 17. Revision history
- 74AVC16T245BQ changed to 74AVC16T245BX for HXQFN60U (SOT1134-1) package. 74AVC16T245 v.2 20100330 Product data sheet - 74AVC16T245 v.1 Modifications:
- 74AVC16T245BQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. 74AVC16T245 v.1 20091001 Product data sheet - -
Product data sheet Rev. 3 — 9 June 2011 26 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state 16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 3 — 9 June 2011 27 of 28 NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AVC16T245 16-bit dual supply translating transceiver; 3-state © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 June 2011 Document identifier: 74AVC16T245 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 12 Typical propagation delay characteristics . . 17