74AVC16835DGGRE4

SN74AVC16835_08 TI1 | Alldatasheet

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18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Member of the Texas Instruments Widebus  Family /C0068 DOC  (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation /C0068 Dynamic Drive Capability Is Equivalent to Standard Outputs With I OH and IOL of ±24 mA at 2.5-V VCC /C0068 Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications /C0068 Ioff Supports Partial-Power-Down Mode Operation /C0068 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) /C0068 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

description

A Dynamic Output Control (DOC ) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V OL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009. 136 –128–144–160 0.4 0.8 1.2 1.6 2.0 2.4 2.8 17015311910285685134170 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 TA = 25°C Process = Nominal IOL – Output Current – mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V – Output Voltage – VOLV TA = 25°C Process = Nominal IOH – Output Current – mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V – Output Voltage – VOHV Figure 1. Output Voltage vs Output Current is high, the outputs are in the high-impedance state. resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. preventing damaging current backflow through the device when it is powered down. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC and Widebus are trademarks of Texas Instruments.

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002

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(TOP VIEW) NC NC GND VCC GND Y10 Y11 Y12 GND Y13 Y14 Y15 V CC Y16 Y17 GND Y18 OE LE GND NC GND V CC GND A10 A11 A12 GND A13 A14 A15 V CC A16 A17 GND A18 CLK GND NC – No internal connection

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING 40°Ct o8 5°C TSSOP – DGG Tape and reel SN74AVC16835DGGR AVC16835 –40°C to 85°C TVSOP – DGV Tape and reel SN74AVC16835DGVR CVA835 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE (each universal bus driver) INPUTS OUTPUT OE LE CLK A Y H X X X Z L HXL L L HXH H L L ↑ LL L L ↑ HH L L L or H X Y0† † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low logic diagram (positive logic) OE CLK CLK To 17 Other Channels LE

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance or power-off state, VO Voltage range applied to any output in the high or low state, VO † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage Operating 1.4 3.6 VVCC Supply voltage Data retention only 1.2 V VCC = 1.2 V VCC VCC = 1.4 V to 1.6 V 0.65 × VCC VIH High-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC V VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 2 VCC = 1.2 V GND VCC = 1.4 V to 1.6 V 0.35 × VCC VIL Low-level input voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VI Input voltage 0 3.6 V VO Output voltage Active state 0 VCC VVO Output voltage 3-state 0 3.6 V VCC = 1.4 V to 1.6 V –2 IOHS Static high level output current† VCC = 1.65 V to 1.95 V –4 mAIOHS Static high-level output current† VCC = 2.3 V to 2.7 V –8 mA VCC = 3 V to 3.6 V –12 VCC = 1.4 V to 1.6 V 2 IOLS Static low level output current† VCC = 1.65 V to 1.95 V 4 mAIOLS Static low-level output current† VCC = 2.3 V to 2.7 V 8 mA VCC = 3 V to 3.6 V 12 ∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature –40 85 °C † Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC . See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006 , and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009 . NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP † MAX UNIT IOHS = –100 µA, 1.4 V to 3.6 VVCC –0.2 IOHS = –2 mA, VIH = 0.91 V 1.4 V 1.05 VOH IOHS = –4 mA, VIH = 1.07 V 1.65 V 1.2 V IOHS = –8 mA, VIH = 1.7 V 2.3 V 1.75 IOHS = –12 mA, VIH = 2 V 3 V 2.3 IOLS = 100 µA 1.4 V to 3.6 V 0.2 IOLS = 2 mA, VIL = 0.49 V 1.4 V 0.4 VOL IOLS = 4 mA, VIL = 0.57 V 1.65 V 0.45 V IOLS = 8 mA, VIL = 0.7 V 2.3 V 0.55 IOLS = 12 mA, VIL = 0.8 V 3 V 0.7 II VI = VCC or GND 3.6 V ±2.5 µA Ioff VI or VO = 3.6 V 0 ±10 µA IOZ VO = VCC or GND, OE = VCC 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA CLK input VI=V CC or GND

2.5 V 4

CLK input VI = VCC or GND

3.3 V 4

C i Control inputs VI=V CC or GND pFC i Control inputs VI = VCC or GND Data inputs VI=V CC or GND 2.5 V 2.5 Data inputs VI = VCC or GND 3.3 V 2.5 C o Outputs VO =V CC or GND 2.5 V 6.5 pFC o Out uts VO = VCC or GND 3.3 V 6.5 F † Typical values are measured at TA = 25°C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency 150 150 150 MHz t Pulse LE high 3.3 3.3 3.3 nstw duration CLK high or low 3.3 3.3 3.3 ns St Data before CLK↑ 1 0.9 0.7 0.7 0.7 tsu Setup before LE↓ CLK low 2 0.9 0.7 0.5 0.5 Hl d Data after CLK↑ 1.5 1.3 1 0.9 1.3 th Hold time Data CLK high 3.2 2.4 2 1.7 1.6 nstime

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNIT(INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX fmax 150 150 150 MHz switching characteristics, TA = 0°C to 85°C, CL = 0 pF† PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.15 V UNIT(INPUT) (OUTPUT) MIN MAX t d A Y 0.6 1.3 nstpd CLK Y 0.7 1.5 ns † Texas Instruments SPICE simulation data operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V UNITPARAMETER TEST CONDITIONS TYP TYP TYP UNIT C d Power dissipation Outputs enabled C L =0 f=1 0M H z 45 48 52 pFC pd capacitance Outputs disabled C L = 0, f = 10 MHz 23 25 28 pF

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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms

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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AVC16835DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16835DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16835DGVRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16835DGVRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16835DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16835DGVR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC16835DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74AVC16835DGVR TVSOP DGV 56 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

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applications

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