74AVC16374DGGRE4

SN74AVC16374_06 TI | Alldatasheet

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FEATURES

136 −128−144−160 0.4 0.8 1.2 1.6 2.0 2.4 2.8 17015311910285685134170 0.4 0.8 1.2 1.6 2.0 2.4 2.8

3.2 TA = 25° C

Process = Nominal IOL − Output Current − mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V − Output Voltage − VOLV TA = 25° C Process = Nominal IOH − Output Current − mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V − Output Voltage − VOHV SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Member of the Texas Instruments Widebus Family I off Supports Partial-Power-Down Mode Operation EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) DOC (Dynamic Output Control) Circuit 200-V Machine Model (A115-A) Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Latch-Up Performance Exceeds 100 mA Per Degradation JESD 78, Class II Dynamic Drive Capability Is Equivalent to Package Options Include Plastic Thin Shrink Standard Outputs With I OH and I OL of mA Small-Outline (DGG) and Thin Very at 2.5-V V CC Small-Outline (DGV) Packages A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure shows typical V OL vs I OL and V OH vs I OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and

Applications

SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and SCEA009. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP DGG Tape and reel SN74AVC16374DGGR AVC16374 C to C TVSOP DGV Tape and reel SN74AVC16374DGVR CVA374 VFBGA GQL Tape and reel SN74AVC16374GQLR CVA374 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Figure Output Voltage vs Output Current Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Widebus, EPIC, DOC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1998 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2 3 4 5 6 SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V V CC but is designed specifically for 1.65-V to 3.6-V V CC operation. The SN74AVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down Ioff. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16374 is characterized for operation from C to TERMINAL ASSIGNMENTS (1) A OE NC NC NC NC 1CLK B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 V CC V CC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 V CC V CC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K OE NC NC NC NC 2CLK (1) NC No internal connection

www.ti.com DGG OR DGV PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 V CC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 V CC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1CLK 1D1 1D2 GND 1D3 1D4 V CC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 V CC 2D5 2D6 GND 2D7 2D8 2CLK SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 FUNCTION TABLE (EACH 8-BIT FLIP FLOP) INPUTS OUTPUT Q OE CLK D L H H L L L L H or L X Q H X X Z

www.ti.com LOGIC SYMBOL (1) (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1OE 2OE 1EN 1CLK 1D1 1D2 1D3 1D4 1Q1 1Q2 1Q3 1Q4 1D5 1D6 1D7 1D8 1Q5 1Q6 1Q7 1Q8 2D1 2D2 2D3 2D4 2Q1 2Q2 2Q3 2Q4 2D5 2D6 2D7 2D8 2Q5 2Q6 2Q7 2Q8 2EN 2CLK 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels 132C1 SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC)

www.ti.com Absolute Maximum Ratings (1) SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 4.6 V V I Input voltge range (2) 0.5 4.6 V V O Voltage range applied to any output in the high-impedance or power-off state (2) 0.5 4.6 V V O Voltage range applied to any output in the high or low state (2) (3) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through each V CC or GND 100 mA DGG package θ JA Package thermal impedance (4) DGV package C/W GQL package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings is observed. (4) The package thermal impedance is calculated in accordance with JESD 51.

www.ti.com Recommended Operating Conditions (1) SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 MIN MAX UNIT Operating 1.4 3.6 V CC Supply voltage V Data retention only 1.2 V CC 1.2 V V CC V CC 1.4 V to 1.6 V 0.65 V CC V IH High-level input voltage V CC 1.65 V to 1.95 V 0.65 V CC V V CC 2.3 V to 2.7 V 1.7 V CC V to 3.6 V V CC 1.2 V GND V CC 1.4 V to 1.6 V 0.35 V CC V IL Low-level input voltage V CC 1.65 V to 1.95 V 0.35 V CC V V CC 2.3 V to 2.7 V 0.7 V CC V to 3.6 V 0.8 V I Input voltage 3.6 V Active state V CC V O Output voltage V 3-state 3.6 V CC 1.4 V to 1.6 V V CC 1.65 V to 1.95 V I OHS Static high-level output current (2) mA V CC 2.3 V to 2.7 V V CC V to 3.6 V V CC 1.4 V to 1.6 V V CC 1.65 V to 1.95 V I OLS Static low-level output current (2) mA V CC 2.3 V to 2.7 V V CC V to 3.6 V Δ Δ v Input transition rise or fall rate V CC 1.4 V to 3.6 V ns/V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. (2) Dynamic drive capability is equivalent to standard outputs with I OH and I OL of mA at 2.5-V V CC See Figure for V OL vs I OL and V OH vs I OH characteristics. Refer to the TI application reports, AVC Logic Family Technology and SCEA006, and Dynamic Output Control DOC Circuitry Technology and SCEA009.

www.ti.com Electrical Characteristics Timing Requirements Switching Characteristics SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OHS 100 µ A 1.4 V to 3.6 V V CC 0.2 I OHS mA, V IH 0.91 V 1.4 V 1.05 V OH I OHS mA, V IH 1.07 V 1.65 V 1.2 V I OHS mA, V IH 1.7 V 2.3 V 1.75 I OHS mA, V IH V V 2.3 I OLS 100 µ A 1.4 V to 3.6 V 0.2 I OLS mA, V IL 0.49 V 1.4 V 0.4 V OL I OLS mA, V IL 0.57 V 1.65 V 0.45 V I OLS mA, V IL 0.7 V 2.3 V 0.55 I OLS mA, V IL 0.8 V V 0.7 I I V I V CC or GND 3.6 V 2.5 µ A I off V I or V O 3.6 V µ A I OZ V O V CC or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A 2.5 V Control inputs V I V CC or GND 3.3 V C i pF 2.5 V 2.5 Data inputs V I V CC or GND 3.3 V 2.5 2.5 V 6.5 C o Outputs V O V CC or GND pF 3.3 V 6.5 (1) Typical values are measured at V CC 2.5 V and 3.3 T A over recommended operating free-air temperature range (unless otherwise noted) V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 3.3 V V CC 1.2 V 0.1 V 0.15 V 0.2 V 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX f clock Clock frequency 160 200 200 MHz t w Pulse duration, CLK high or low 3.1 2.5 2.5 ns t su Setup time, data before CLK 4.1 2.7 1.9 1.4 1.4 ns t h Hold time, data after CLK 1.7 1.3 1.2 1.1 1.1 ns over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 3.3 V V CC 1.2 V FROM TO 0.1 V 0.15 V 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX f max 160 200 200 MHz t pd CLK Q 7.3 1.5 8.4 1.2 6.7 0.8 4.1 0.7 3.3 ns t en OE Q 7.4 1.6 8.5 1.6 6.7 0.9 4.3 0.7 3.4 ns t dis OE Q 8.4 2.5 9.4 2.3 7.8 4.2 1.5 3.9 ns

www.ti.com Operating Characteristics SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 T A C V CC 1.8 V V CC 2.5 V V CC 3.3 V PARAMETER TEST CONDITIONS UNIT TYP TYP TYP Outputs enabled Power dissipation C pd C L f MHz pF capacitance Outputs disabled

www.ti.com PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2VCC/2 VCC/2VCC/2 VCC/2VCC/2 VOH VOL thtsu From Output Under Test CL = 15 pF (see Note A) LOAD CIRCUIT S1 Open GND 2 kΩ 2 kΩ Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.1 V VOH − 0.1 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤/char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2 ns, tf ≤/char????????2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 V CC 1.2 V AND 1.5 V 0.1 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2VCC/2 VCC/2VCC/2 VCC/2VCC/2 VOH VOL thtsu From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 1 kΩ 1 kΩ Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 V CC 1.8 V 0.15 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2VCC/2 VCC/2VCC/2 VCC/2VCC/2 VOH VOL thtsu From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ /char????????2 ns, tf ≤/char????????2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC/2 tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 V CC 2.5 V 0.2 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION VOH VOL thtsu From Output CL = 30 pF (see Note A) LOAD CIRCUIT 2 × VCC Open GND 500 Ω 500 Ω tPLH tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + 0.3 V VOH − 0.3 V 0 V VCC 0 V 0 V VCC 0 V tw Input VCC VCC VCC VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Output Input tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤/char????????10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤/char????????2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 SN74AVC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES158H DECEMBER 1998 REVISED MARCH 2005 V CC 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AVC16374DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16374DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16374DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16374DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16374GQLR ACTIVE BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74AVC16374ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2006 Addendum-Page 1

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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