74AVC16373DGGRG4

SN74AVC16373_15 TI1 | Alldatasheet

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0.4 0.8 1.2 1.6 2.0 2.4 2.8 17015311910285685134170 0.4 0.8 1.2 1.6 2.0 2.4 2.8

3.2 TA = 25°C

Process = Nominal IOL - Output Current - mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V - Output Voltage - VOLV TA = 25°C Process = Nominal IOH - Output Current - mA VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V - Output Voltage - VOHV SN74AVC16373 www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Overvoltage-Tolerant Inputs/Outputs Allow Family Mixed-Voltage-Mode Data Communications EPIC (Enhanced-Performance Implanted I off Supports Partial-Power-Down Mode CMOS) Submicron Process Operation DOC (Dynamic Output Control) Circuit ESD Protection Exceeds JESD Dynamically Changes Output Impedance, 2000-V Human-Body Model (A114-A) Resulting in Noise Reduction Without Speed 200-V Machine Model (A115-A) Degradation Latch-Up Performance Exceeds 100 mA Per Dynamic Drive Capability Is Equivalent to JESD 78, Class II Standard Outputs With I OH and I OL of mA at Package Options Include Plastic Thin Shrink 2.5-V V CC Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages A Dynamic Output Control (DOC circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure shows typical V OL vs I OL and V OH vs I OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and

Applications

SCEA006, and Dynamic Output Control (DOC Circuitry Technology and SCEA009. Figure Output Voltage vs Output Current This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V V CC but is designed specifically for 1.65-V to 3.6-V V CC operation. The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Widebus, EPIC, DOC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1998 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(CONTINUED) TERMINAL ASSIGNMENTS GQL/ZQL PACKAGE (TOP VIEW) A B C D E F G H J K 43 62 5 DGG OR DGV P ACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 V CC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 V CC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1LE 1D1 1D2 GND 1D3 1D4 V CC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 V CC 2D5 2D6 GND 2D7 2D8 2LE SN74AVC16373 SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 www.ti.com A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down I off The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16373 is characterized for operation from C to TERMINAL ASSIGNMENTS (56-Ball GQL/ZQL Package) (1) A 1DIR NC NC NC NC OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 V CCB V CCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 V CCB V CCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC OE (1) NC No internal connection Submit Documentation Feedback Copyright 1998 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AVC16373

www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 FUNCTION TABLE (EACH 8-BIT LATCH) INPUTS OUTPUT Q OE LE D L H H H L H L L L L X Q H X X Z LOGIC SYMBOL (1) (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (POSITIVE LOGIC) Copyright 1998 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74AVC16373

(1) SN74AVC16373 SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 www.ti.com over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 4.6 V V I Input voltage range (2) 0.5 4.6 V V O Voltage range applied to any output in the high-impedance or power-off state (2) 0.5 4.6 V V O Voltage range applied to any output in the high or low state (2) (3) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through each V CC or GND 100 mA DGG package θ JA Package thermal impedance (4) DGV package C/W GQL/ZQL package T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. (4) The package thermal impedance is calculated in accordance with JESD 51. Submit Documentation Feedback Copyright 1998 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AVC16373

(1) SN74AVC16373 www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 MIN MAX UNIT Operating 1.4 3.6 V CC Supply voltage V Data retention only 1.2 V CC 1.2 V V CC V CC 1.4 V to 1.6 V 0.65 V CC V IH High-level input voltage V CC 1.65 V to 1.95 V 0.65 V CC V V CC 2.3 V to 2.7 V 1.7 V CC V to 3.6 V V CC 1.2 V GND V CC 1.4 V to 1.6 V 0.35 V CC V IL Low-level input voltage V CC 1.65 V to 1.95 V 0.35 V CC V V CC 2.3 V to 2.7 V 0.7 V CC V to 3.6 V 0.8 V I Input voltage 3.6 V Active state V CC V O Output voltage V 3-state 3.6 V CC 1.4 V to 1.6 V V CC 1.65 V to 1.95 V I OHS Static high-level output current (2) mA V CC 2.3 V to 2.7 V V CC V to 3.6 V V CC 1.4 V to 1.6 V V CC 1.65 V to 1.95 V I OLS Static low-level output current (2) mA V CC 2.3 V to 2.7 V V CC V to 3.6 V Δ Δ v Input transition rise or fall rate V CC 1.4 V to 3.6 V ns/V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. (2) Dynamic drive capability is equivalent to standard outputs with I OH and I OL of mA at 2.5-V V CC See Figure for V OL vs I OL and V OH vs I OH characteristics. Refer to the TI application reports, AVC Logic Family Technology and SCEA066, and Dynamic Output Control (DOC Circuitry Technology and SCEA009. Copyright 1998 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74AVC16373

www.ti.com over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OHS 100 µ A 1.4 V to 3.6 V V CC 0.2 I OHS mA, V IH 0.91 V 1.4 V 1.05 V OH I OHS mA, V IH 1.07 V 1.65 V 1.2 V I OHS mA, V IH 1.7 V 2.3 V 1.75 I OHS mA, V IH V V 2.3 I OLS 100 µ A 1.4 V to 3.6 V 0.2 I OLS mA, V IL 0.49 V 1.4 V 0.4 V OL I OLS mA, V IL 0.57 V 1.65 V 0.45 V I OLS mA, V IL 0.7 V 2.3 V 0.55 I OLS mA, V IL 0.8 V V 0.7 I I V I V CC or GND 3.6 V 2.5 µ A I off V I or V O 3.6 V µ A I OZ V O V CC or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A 2.5 V Control inputs V I V CC or GND 3.3 V C i pF 2.5 V 2.5 Data inputs V I V CC or GND 3.3 V 2.5 2.5 V 6.5 C o Outputs V O V CC or GND pF 3.3 V 6.5 (1) Typical values are measured at V CC 2.5 V and 3.3 T A over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 3.3 V V CC 1.2 V 0.1 V 0.15 V 0.2 V 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t w Pulse duration, LE high 2.2 1.8 ns t su Setup time, data before LE 1.7 1.2 1.1 0.9 0.8 ns t h Hold time, data after LE 1.1 1.1 1.1 ns over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 3.3 V V CC 1.2 V FROM TO 0.1 V 0.15 V 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX D 5.8 1.2 6.8 5.7 0.8 3.3 0.7 2.8 t pd Q ns LE 7.2 1.4 8.3 1.1 6.6 0.8 0.7 3.2 t en OE Q 7.4 1.6 8.8 1.6 6.7 1.4 4.3 0.7 3.4 ns t dis OE Q 8.4 2.5 9.4 2.3 7.8 1.3 4.2 1.2 3.9 ns Submit Documentation Feedback Copyright 1998 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AVC16373

www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 T A C V CC 1.8 V V CC 2.5 V V CC 3.3 V PARAMETER TEST CONDITIONS UNIT TYP TYP TYP Outputs enabled Power dissipation C pd C L f MHz pF capacitance Outputs disabled Copyright 1998 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74AVC16373

C L = 15 pF (see Note A) LOAD CIRCUIT S1 Open GND 2 kW 2 kW Output Control (low-level enabling) Output W aveform 1 S1 at 2 × VCC (see Note B) Output W aveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.1 V VOH − 0.1 V 0 V VCC 0 V 0 V tw VCC VCC VOLT AGE W AVEFORMS SETUP AND HOLD TIMES VOLT AGE W AVEFORMS PULSE DURA TION VOLT AGE W AVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND TEST S1 NOTES: A. C L includes probe and jig capacitance. B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. W aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr10 MHz, ZO = 50 W , tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 ns, tf ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC /2 tPHL VCC /2 V CC /2 VCC 0 V VOH VOL Input Output VOLT AGE W AVEFORMS PROPAGA TION DELA Y TIMES VCC /2 V CC /2 tPLH 2 × VCC VCC SN74AVC16373 SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 www.ti.com V CC 1.2 V AND 1.5 V 0.1 V Figure Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright 1998 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AVC16373

C L = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 1 kW 1 kW Output Control (low-level enabling) Output W aveform 1 S1 at 2 × VCC (see Note B) Output W aveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLT AGE W AVEFORMS SETUP AND HOLD TIMES VOLT AGE W AVEFORMS PULSE DURA TION VOLT AGE W AVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND TEST S1 NOTES: A. C L includes probe and jig capacitance. B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC /2 tPHL VCC /2 V CC /2 VCC 0 V VOH VOL Input Output VOLT AGE W AVEFORMS PROPAGA TION DELA Y TIMES VCC /2 V CC /2 tPLH 2 × VCC VCC SN74AVC16373 www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 V CC 1.8 V 0.15 V Figure Load Circuit and Voltage Waveforms Copyright 1998 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74AVC16373

C L = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 W 500 W Output Control (low-level enabling) Output W aveform 1 S1 at 2 × VCC (see Note B) Output W aveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V VCC 0 V 0 V tw VCC VCC VOLT AGE W AVEFORMS SETUP AND HOLD TIMES VOLT AGE W AVEFORMS PULSE DURA TION VOLT AGE W AVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND TEST S1 NOTES: A. C L includes probe and jig capacitance. B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. W aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 ns, tf ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. 0 V VCC VCC /2 tPHL VCC /2 V CC /2 VCC 0 V VOH VOL Input Output VOLT AGE W AVEFORMS PROPAGA TION DELA Y TIMES VCC /2 V CC /2 tPLH 2 × VCC VCC SN74AVC16373 SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 www.ti.com V CC 2.5 V 0.2 V Figure Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright 1998 2008, Texas Instruments Incorporated Product Folder Link(s): SN74AVC16373

/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrUnder Test C L = 30 pF (see Note A) LOAD CIRCUIT 2 × VCC Open GND 500 W 500 W tPLH tPHL Output Control (low-level enabling) Output W aveform 1 S1 at 2 × VCC (see Note B) Output W aveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCC 0 V VOH VOL 0 V VOL + 0.3 V VOH − 0.3 V 0 V VCC 0 V 0 V VCC 0 V tw Input VCC VCC VCC VOLT AGE W AVEFORMS SETUP AND HOLD TIMES VOLT AGE W AVEFORMS PROPAGA TION DELA Y TIMES VOLT AGE W AVEFORMS PULSE DURA TION VOLT AGE W AVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Output Input tpd tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND TEST S1 NOTES: A. C L includes probe and jig capacitance. B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. W aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr10 MHz, ZO = 50 W , tr ≤ 2 ns, tf ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. VCC /2 VCC /2 V CC /2 VCC /2 V CC /2 VCC /2 VCC /2 VCC /2 V CC /2 VCC /2 VCC /2 VCC /2 VCC /2 SN74AVC16373 www.ti.com SCES156H DECEMBER 1998 REVISED SEPTEMBER 2008 V CC 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms Copyright 1998 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74AVC16373

www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 74AVC16373DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16373 SN74AVC16373DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16373 SN74AVC16373DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CVA373 SN74AVC16373ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 CVA373 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 24-Apr-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SN74AVC16373ZQLR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC16373DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74AVC16373DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74AVC16373ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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