74AVC16373

74AVC16373 PHILIPS | Alldatasheet

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Technical content

Product Specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC24

2000 Mar 09

16-bit D-type transparent latch;

3.6 V tolerant; 3-state

2000 Mar 09 2

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373

FEATURES

• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
• Low inductance multiple V CC and GND pins to minimize noise and ground bounce
• Supports Live Insertion.

DESCRIPTION

The 74AVC16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch, and 3-state outputs for bus oriented applications. One Latch Enable (LE) input and one Output Enable ( OE) input are provided per 8-bit section. The 74AVC16373 consist of two sections of eight D-type transparent latches with 3-state true outputs. The 74AVC16373 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, pin OE n should be tied to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figs 1 and 2).handbook, halfpage 012 4 −200 −300 −100 MNA506

3 VOH (V)

(mA) 1.8 V 2.5 V 3.3 V Fig.1 Output voltage as a function of the HIGH-level output current. handbook, halfpage 012 4 300 100 200 MNA507

3 VOL (V)

(mA) 1.8 V 2.5 V 3.3 V Fig.2 Output voltage as a function of the LOW-level output current.

2000 Mar 09 3

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf≤ 2.0 ns. Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW). PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz; fo = output frequency in MHz; C L = output load capacitance in pF; VCC = supply voltage in Volts; ∑ (CL × VCC 2 × fo) = sum of outputs. 2. The condition is VI= GND to VCC . FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high impedance OFF-state. SYMBOL PARAMETER CONDITIONS TYP. UNIT t PHL /tPLH propagation delay nD n to nQn VCC = 1.2 V 3.6 ns VCC = 1.5 V 3.1 ns VCC = 1.8 V 2.2 ns VCC = 2.5 V 1.6 ns VCC = 3.3 V 1.4 ns C I input capacitance 5.0 pF C PD power dissipation capacitance per buffer notes 1 and 2 outputs enabled 34 pF outputs disabled 1 pF OPERATING MODES INPUTS INTERNAL LATCHES OUTPUTS n OE LE nA n nY n Enable and read register (transparent mode) L L H H L H L H L H Latch and read register (hold mode) L L L L l h L H L H Latch register and disable outputs H H L L l h L H Z Z

2000 Mar 09 4

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 ORDERING AND PACKAGE INFORMATION PINNING TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74AVC16373DGG −40 to +85°C 48 TSSOP plastic SOT362-1 PIN SYMBOL DESCRIPTION

11 OE output enable input (active LOW)

2, 3, 5, 6, 8, 9, 11 and 12 1Q 0 to 1Q7 data outputs 4, 10, 15, 21, 28, 34, 39 and 45 GND ground (0 V) 7, 18, 31 and 42 V CC DC supply voltage 13, 14, 16, 17, 19, 20, 22 and 23 2Q 0 to 2Q7 data outputs 24 2 OE output enable input (active LOW) 25 2LE latch enable input (active HIGH) 26, 27, 29, 30, 32, 33, 35 and 36 2D 7 to 2D0 data inputs 37, 38, 40, 41, 43, 44, 46 and 47 1D 7 to 1D0 data inputs 48 1LE latch enable input (active HIGH)

2000 Mar 09 5

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 handbook, halfpage 16373 MNA541 1OE 1Q 0 1Q 1 GND 1Q 2 1Q 3 VCC 1Q 4 1Q 5 GND 1Q 6 1Q 7 2Q 0 2Q 1 GND 2Q 2 2Q 3 VCC 2Q 4 2Q 5 GND 2Q 6 2Q 7 2OE 1LE 1D 0 1D 1 GND 1D 2 1D 3 VCC 1D 4 1D 5 GND 1D 6 1D 7 2D 0 2D 1 GND 2D 2 2D 3 VCC 2D 4 2D 5 GND 2D 6 2D 7 2LE Fig.3 Pin configuration. handbook, halfpage MNA547 1Q 0 1Q 1 1LE 2LE 1Q 2 1Q 3 1Q 4 1Q 5 1Q 6 1Q 7 1OE 48 25 2Q 0 2Q 1 2Q 2 2Q 3 2Q 4 2Q 5 2Q 6 2Q 7 1D 0 1D 1 1D 2 1D 3 1D 4 1D 5 1D 6 1D 7 2D 0 2D 1 2D 2 2D 3 2D 4 2D 5 2D 6 2D 7 2OE Fig.4 Logic symbol.

2000 Mar 09 6

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 handbook, halfpage MNA546 37 12 1D 7 1D 0 1D 1 1D 2 1D 3 1D 4 1D 5 1D 6 1Q 7 1Q 6 1Q 5 1Q 4 1Q 3 1Q 2 1Q 0 1Q 1 2D 5 2D 0 2D 1 2D 2 2D 3 2D 4 2Q 5 2Q 4 2Q 3 2Q 2 2Q 1 2Q 0 2EN 1OE 1 1EN 1LE 2OE 2LE 48 C3 3D 1 4D 2 2D 7 2D 6 2Q 7 2Q 6 Fig.5 IEEE/IEC logic symbol. handbook, full pagewidth MNA545 D1 Q 01D 0 1LE 1OE Q LE LATCH to 7 other channels D2 Q 02D 0 2LE 2OE Q LE LATCH to 7 other channels Fig.6 Logic diagram.

2000 Mar 09 7

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 RECOMMENDED OPERATING CONDITIONS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60°C the value of P D derates linearly with 5.5 mW/K. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage according to JEDEC Low Voltage Standards 1.4 1.6 V 1.65 1.95 V 2.3 2.7 V 3.0 3.6 V for low-voltage applications 1.2 3.6 V V I DC input voltage 0 3.6 V VO DC output voltage output 3-state 0 3.6 V output HIGH or LOW state 0 V CC V Tamb operating ambient temperature in free air −40 +85 °C tr,tf input rise and fall time ratios VCC = 1.4 to 1.6 V 0 40 ns/V VCC = 1.65 to 2.3 V 0 30 ns/V VCC = 2.3 to 3.0 V 0 20 ns/V VCC = 3.0 to 3.6 V 0 10 ns/V SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +4.6 V IIK DC input diode current V I<0 −− 50 mA VI DC input voltage for inputs; note 1 −0.5 +4.6 V IOK DC output clamping diode current VO <0 −− 50 mA VO DC output voltage output HIGH or LOW state; note 1 −0.5 V CC + 0.5 V output 3-state; note 1 −0.5 +4.6 V IO DC output sink current V O = 0 to VCC − 50 mA ICC ,IGND DC V CC or GND current −± 100 mA Tstg storage temperature −65 +150 °C PD power dissipation per package for temperature range: −40 to +85°C; note 2 − 500 mW

2000 Mar 09 8

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground=0V ) . Note 1. All typical values are measured at Tamb =2 5°C. SYMBOL PARAMETER TEST CONDITIONS T amb = −40 to +85°C UNIT OTHER V CC (V) MIN. TYP. (1) MAX. VIH HIGH-level input voltage

1.2 V CC −− V

1.4 to 1.6 0.65× VCC 0.9 − V 1.65 to 1.95 0.65× VCC 0.9 − V 2.3 to 2.7 1.7 1.2 − V 3.0 to 3.6 2.0 1.5 − V VIL LOW-level input voltage 1.2 −− GND V 1.4 to 1.6 − 0.9 0.35 × VCC V 1.65 to 1.95− 0.9 0.35 × VCC V 2.3 to 2.7 − 1.2 0.7 V 3.0 to 3.6 − 1.5 0.8 V VOH HIGH-level output voltage VI=V IH or VIL IO = −100 µA 1.65 to 3.6 V CC − 0.20 V CC − V IO = −3 mA 1.4 V CC − 0.35 V CC − 0.23 − V IO = −4 mA 1.65 V CC − 0.45 V CC − 0.25 − V IO = −8 mA 2.3 V CC − 0.55 V CC − 0.38 − V IO = −12 mA 3.0 V CC − 0.70 V CC − 0.48 − V VOL LOW-level output voltage VI=V IH or VIL IO = 100µA 1.65 to 3.6 − GND 0.20 V IO =3m A 1 . 4 − 0.18 0.35 V IO = 4 mA 1.65 − 0.22 0.45 V IO =8m A 2 . 3 − 0.37 0.55 V IO =2m A 3 . 0 − 0.51 0.70 V II input leakage current per pin VI=V CC or GND 1.4 to 3.6 − 0.1 2.5 µA Ioff power-off leakage current VIor VO = 3.6 V 0 − 0.1 ±10 µA IIHZ/IILZ input current for common I/O pins VI=V CC or GND 1.4 to 3.6 − 0.1 12.5 µA IOZ 3-state output OFF −state current VI=V IH or VIL; VO =V CC or GND 1.4 to 2.7 − 0.1 5 µA 3.0 to 3.6 − 0.1 10 µA ICC quiescent supply current VI=V CC or GND; IO =0 1.4 to 2.7 − 0.1 20 µA 3.0 to 3.6 − 0.2 40 µA

2000 Mar 09 9

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 AC CHARACTERISTICS GND = 0 V; tr =tf≤ 2.0 ns. Note SYMBOL PARAMETER TEST CONDITIONS T amb = −40 to +85°C UNIT WAVEFORMS V CC (V) MIN. TYP. (1) MAX. tPHL /tPLH propagation delay nDn to nQn see Figs 7 and 11 1.2 − 3.6 − ns propagation delay nLE to nQ n see Figs 8 and 11 1.2 − 3.6 − ns t PZH /tPZL 3-state output enable time nOE to nQn see Figs 9 and 11 1.2 − 5.9 − ns t PHZ /tPLZ 3-state output disable time nOE to nQn see Figs 9 and 11 1.2 − 5.8 − ns t W nLE pulse width HIGH see Figs 8 and 11 1.2 − 2.4 − ns 1.40 to 1.60− 1.9 − ns 1.65 to 1.95 2.2 1.7 − ns 2.3 to 2.7 2.0 1.6 − ns 3.0 to 3.6 1.8 1.4 − ns tsu set-up time nDn to nLE see Figs 10 and 11 1.2 − 0.4 − ns 1.40 to 1.60 1.2 0.2 − ns 1.65 to 1.95 1.1 0.1 − ns th hold time nDn to nLE see Figs 10 and 11 1.2 −− 0.2 − ns 1.65 to 1.95 1.1 0.0 − ns 2.3 to 2.7 1.1 0.1 − ns 3.0 to 3.6 1.0 0.2 − ns

2000 Mar 09 10

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 AC WAVEFORMS handbook, full pagewidth MNA544 tPLHtPHL VM VM nQ n output nD n input GND VI VOH VOL Fig.7 The input (nDn) to output (nQn) propagation delay. VCC VM VI ≤2.3 to 2.7 V 0.5× VCC VCC 3.0 to 3.6 V 0.5× VCC VCC VOL and VOH are typical output voltage drop that occur with the output load. handbook, full pagewidth MNA543 tPHL tPLHtW VM VM VMnLE input nQ n output GND VI VOH VOL Fig.8 The latch enable input (nLE) pulse width to output (nQn) propagation delays. VCC VM VI ≤2.3 to 2.7 V 0.5× VCC VCC 3.0 to 3.6 V 0.5× VCC VCC VOL and VOH are typical output voltage drop that occur with the output load.

2000 Mar 09 11

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 handbook, full pagewidth MNA478 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Fig.9 3-state enable and disable times. VCC VM VX VY VI VOL and VOH are typical output voltage drop that occur with the output load. handbook, full pagewidth MNA542 th tsu th tsu VM VM VI GND VI GND nLE input nD n input Fig.10 Data set-up and hold times for nDn input to nLE input. VCC VM VI ≤2.3 to 2.7 V 0.5× VCC VCC 3.0 to 3.6 V 0.5× VCC VCC The shaded areas indicate when the input is permitted to change for predictable output performance.

2000 Mar 09 12

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 handbook, full pagewidth open GND 2 × VCC VCC VI VO MNA505 D.U.T. C LR T R load R load PULSE GENERATOR Fig.11 Load circuitry for switching times. TEST S1 tPLH /tPHL open tPLZ /tPZL 2 × VCC tPHZ /tPZH GND VCC (V) V I R load C L

1.2 V CC 2000 Ω 15 pF

1.4 to 1.6 V CC 2000 Ω 15 pF 1.65 to 1.95 VCC 1000 Ω 30 pF 2.3 to 2.7 V CC 500 Ω 30 pF 3.0 to 3.6 V CC 500 Ω 30 pF

2000 Mar 09 13

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 PACKAGE OUTLINE UNIT A 1 A 2 A 3 bp cD (1) E (2) eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.15 0.05 0.2 0.1 o o0.1 DIMENSIONS (mm are the original dimensions). Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. SOT362-1 95-02-10 99-12-27 w M θ AA 1 A 2 D Lp Q detail X E Z e c L X (A )3 0.25 12 4 48 25 y pin 1 index b H 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.258.3 7.9 0.50 0.35 0.8 0.40.080.8 0.4 p E v M A A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 A max. 1.2 0 2.5 5 mm scale MO-153

2000 Mar 09 14

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250°C. The top-surface temperature of the packages should preferable be kept below 230°C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis ispreferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

2000 Mar 09 15

Philips Semiconductors Product Specification 16-bit D-type transparent latch; 3.6 V tolerant; 3-state 74AVC16373 Suitability of surface mount IC packages for wave and reflow soldering methods Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PACKAGE SOLDERING METHOD WAVE REFLOW (1) BGA, LFBGA, SQFP , TFBGA not suitable suitable HBCC, HLQFP , HSQFP , HSOP , HTQFP , HTSSOP , SMS not suitable (2) suitable PLCC (3), SO, SOJ suitable suitable LQFP , QFP , TQFP not recommended (3)(4) suitable SSOP , TSSOP , VSO not recommended (5) suitable Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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