74AUP1G07GF | DigiCamel IC Datasheet

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Technical content

General description The 74AUP1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully speciﬁed for partial Power-down applications using IOFF . The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G07 provides the single non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114E Class 3A exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101C exceeds 1000 V ■ Low static power consumption; ICC = 0.9µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Speciﬁed from−40 °Ct o+ 8 5°C and −40 °C to +125°C 74AUP1G07 Low-power buffer with open-drain output Rev. 02 — 14 June 2007 Product data sheet

6.1 Pinning

6.2 Pin description

Z = high-impedance OFF state. Table 3. Pin description Table 4. Function table[1]

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 packages: above 87.5°C the value of Ptotderates linearly with 4.0 mW/K. For XSON6 packages: above 45°C the value of Ptotderates linearly with 2.4 mW/K.

Recommended operating conditions

Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 6. Recommended operating conditions

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure8.

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. [1] All typical values are measured at nominal VCC . [2] tpd is the same as tPZL and tPLZ . [3] C PD is used to determine the dynamic power dissipation (PD inµW). L × VCC 2 × fo) = sum of the outputs. Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure8. Measurement points are given inTable9. Logic level: VOL is the typical output voltage drop that occur with the output load. Table 9. Measurement points

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. [1] For measuring enable and disable times RL =5k Ω , for measuring propagation delays, setup and hold times and pulse width RL =1M Ω . Test data is given inTable10. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Table 10. Test data

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 14 June 2007 11 of 16 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output 13. Package outline Fig 9. Package outline SOT353-1 (TSSOP5) UNIT A 1 A max. A 2 A 3 bp LH E Lp wyvce D (1) E(1) Z(1) q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.1 1.0 0.8 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.60 0.15 0°0.1 0.10.30.425 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.46 0.21 SOT353-1 MO-203 SC-88A 00-09-01 03-02-19 w Mbp D Z e 0.15 5 4 q AA2 Lp (A3) detail X L H E E c v M A X A y 1.5 3 mm0 scale TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 1.1

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 14 June 2007 12 of 16 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output Fig 10. Package outline SOT886 (XSON6) terminal 1 index area REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT886 MO-252 SOT886 04-07-15 04-07-22 DIMENSIONS (mm are the original dimensions) XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm D E e A 1 b LL1 0 1 2 mm scale Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. UNIT mm 0.25 0.17 1.5 1.4 0.35 0.27 A max b E 1.05 0.95 D ee 1 L 0.40 0.32 0.50.6 A (1) max 0.5 0.04 (2) (2) A

74AUP1G07_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 14 June 2007 13 of 16 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output Fig 11. Package outline SOT891 (XSON6) terminal 1 index area REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT891 SOT891 05-04-06 07-05-15 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm D E e A 1 b LL1 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm 0.20 0.12 1.05 0.95 0.35 0.27 A 1 max b E 1.05 0.95 D ee 1 L 0.40 0.32 0.350.55 A max 0.5 0.04 A6× (1) (1) Note 1. Can be visible in some manufacturing processes.

Added IOZ inSection10,Table7 74AUP1G07_1 20061010 Product data sheet - -

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: sales.addresses@www.nxp.com Date of release: 14 June 2007 Document identifier: 74AUP1G07_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents

Product Information

74AUP1G07GF specifications and overview.

Summary

Low-power buffer with open-drain output Rev. 02-14 June 2007

Description

Low-power buffer with open-drain output Rev. 02-14 June 2007

Source title 74AUP1G07GF Datasheet(PDF) - NXP Semiconductors

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