74AUC1GU04DBVRE4

SN74AUC1GU04_10 TI | Alldatasheet

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Y A GND DBV□PACKAGE (TOP□VIEW) YZP□PACKAGE (BOTTOM□VIEW) DCK□PACKAGE (TOP□VIEW) 51NC V CC Y A GND DNU GND VCC Y A NC – No□internal□connection See□mechanical□drawings□for□dimensions. DNU Do□not□use/c45 DRY P ACKAGE (TOP VIEW) A NC NC 6 3GND Y VCC1 PREVIE W DESCRIPTION/ORDERING INFORMATION SN74AUC1GU04 SINGLE INVERTER GATE SCES371L SEPTEMBER 2001 REVISED APRIL 2007 Available in the Texas Instruments 8-mA Output Drive at 1.8 V NanoFree Package Unbuffered Output Optimized for 1.8-V Operation and Is 3.6-V I/O Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, Class II Operation ESD Protection Exceeds JESD Sub-1-V Operable 2000-V Human-Body Model (A114-A) Max t pd of 2.4 ns at 1.8 V 200-V Machine Model (A115-A) Low Power Consumption, 10- µ A Max I CC 1000-V Charged-Device Model (C101) This single inverter gate is operational at 0.8-V to 2.7-V V CC but is designed specifically for 1.65-V to 1.95-V V CC operation. The SN74AUC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y A NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION ORDERABLE PART T A PACKAGE (1) (2) TOP-SIDE MARKING (3) NUMBER NanoFree WCSP (DSBGA) Reel of 3000 SN74AUC1GU04YZPR _UD_ 0.23-mm Large Bump YZP (Pb-free) C to C SON DRY Reel of 5000 SN74AUC1GU04DRYR PREVIEW SOT (SOT-23) DBV Reel of 300 SN74AUC1GU04DBVR UU4_ SOT (SC-70) DCK Reel of 300 SN74AUC1GU04DCKR UD_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. NanoFree is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains Copyright 2001 2007, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com A Y 2 4 Absolute Maximum Ratings (1) SN74AUC1GU04 SINGLE INVERTER GATE SCES371L SEPTEMBER 2001 REVISED APRIL 2007 FUNCTION TABLE INPUT OUTPUT A Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 3.6 V V I Input voltage range (2) 0.5 3.6 V V O Output voltage range (2) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through V CC or GND 100 mA DBV package 206 DCK package 252 θ JA Package thermal impedance (3) C/W DRY package 234 YZP package 132 T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback

www.ti.com Recommended Operating Conditions (1) Electrical Characteristics SN74AUC1GU04 SINGLE INVERTER GATE SCES371L SEPTEMBER 2001 REVISED APRIL 2007 MIN MAX UNIT V CC Supply voltage 0.8 2.7 V V IH High-level input voltage I O 100 µ A 0.65 V CC V V IL Low-level input voltage I O 100 µ A 0.35 V CC V V I Input voltage 3.6 V V O Output voltage V CC V V CC 0.8 V 0.7 V CC 1.1 V I OH High-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V V CC 0.8 V 0.7 V CC 1.1 V I OL Low-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V Δ Δ v Input transition rise or fall rate ns/V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH 100 µ A 0.8 V to 2.7 V V CC 0.1 I OH 0.7 mA 0.8 V 0.55 I OH mA 1.1 V 0.8 V OH V I OH mA 1.4 V I OH mA 1.65 V 1.2 I OH mA 2.3 V 1.8 I OL 100 µ A 0.8 V to 2.7 V 0.2 I OL 0.7 mA 0.8 V 0.25 I OL mA 1.1 V 0.3 V OL V I OL mA 1.4 V 0.4 I OL mA 1.65 V 0.45 I OL mA 2.3 V 0.6 I I A input V I V CC or GND to 2.7 V µ A I CC V I V CC or GND, I O 0.8 V to 2.7 V µ A C i V I V CC or GND 2.5 V pF (1) All typical values are at T A Submit Documentation Feedback

www.ti.com Switching Characteristics Switching Characteristics Operating Characteristics SN74AUC1GU04 SINGLE INVERTER GATE SCES371L SEPTEMBER 2001 REVISED APRIL 2007 over recommended operating free-air temperature range, C L pF (unless otherwise noted) (see Figure V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 0.8 V FROM TO 0.1 V 0.1 V 0.15 V 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX t pd A Y 1.9 0.6 2.5 0.6 1.7 0.3 1.1 2.3 0.2 ns over recommended operating free-air temperature range, C L pF (unless otherwise noted) (see Figure V CC 1.8 V V CC 2.5 V FROM TO 0.15 V 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX t pd A Y 0.6 1.1 2.4 0.5 2.1 ns T A C V CC 0.8 V V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V TEST PARAMETER UNIT CONDITIONS TYP TYP TYP TYP TYP Power dissipation C pd f MHz pF capacitance Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION VCC /2 thtsu From Output Under Test C L (see Note A) LOAD CIRCUIT 2 × VCC Open GND R L R L Data Input Timing Input VCC 0 V VCC 0 V 0 V tw Input VOLT AGE W AVEFORMS SETUP AND HOLD TIMES VOLT AGE W AVEFORMS PROPAGA TION DELA Y TIMES INVERTING AND NONINVERTING OUTPUTS VOLT AGE W AVEFORMS PULSE DURA TION tPLH tPHL tPHL tPLH VOH VOH VOL VOL VCC 0 V Input Output W aveform 1 S1 at 2 × VCC (see Note B) Output W aveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VCC 0 V VOL + VD VOH – VD ≈0 V VCC VOLT AGE W AVEFORMS ENABLE AND DISABLE TIMES LOW - AND HIGH-LEVEL ENABLING Output Output tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND TEST S1 NOTES: A. C L includes probe and jig capacitance. B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Output Control VCC /2 V CC /2 VCC /2 V CC /2 VCC /2 VCC /2 VCC /2 VCC /2 V CC /2 VCC /2 VCC /2 VCC /2 VCC VCC /2 VCC /2 0.8 V 1.2 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.1 V 1.5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.1 V 1.8 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.15 V 2.5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.2 V 1.8 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.15 V 2.5 V ±/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.2 V 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W VCC R L 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VD C L 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF SN74AUC1GU04 SINGLE INVERTER GATE SCES371L SEPTEMBER 2001 REVISED APRIL 2007 Figure Load Circuit and Voltage Waveforms Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AUC1GU04DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUC1GU04DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUC1GU04DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1GU04DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1GU04DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1GU04DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1GU04YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUC1GU04DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUC1GU04DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74AUC1GU04YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 Pack Materials-Page 2

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