74AUC1G125DBVRE4

SN74AUC1G125_07 TI | Alldatasheet

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Y A GND DBV□PACKAGE (TOP VIEW) 51OE VCC Y A GND OE GND Y A See□mechanical□drawings□for□dimensions. DCK□PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM□VIEW) DRY PACKAGE (TOP VIEW) A NC OE 6 3GND Y VCC1 PREVIEW NC – No□internal□connection DESCRIPTION/ORDERING INFORMATION SN74AUC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES382K MARCH 2002 REVISED APRIL 2007 Available in the Texas Instruments Low Power Consumption, 10- µ A Max I CC NanoFree Package 8-mA Output Drive at 1.8 V Optimized for 1.8-V Operation and Is 3.6-V I/O Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, Class II Operation ESD Protection Exceeds JESD I off Supports Partial-Power-Down Mode 2000-V Human-Body Model (A114-A) Operation 200-V Machine Model (A115-A) Sub-1-V Operable 1000-V Charged-Device Model (C101) Max t pd of 2.5 ns at 1.8 V This bus buffer gate is operational at 0.8-V to 2.7-V V CC but is designed specifically for 1.65-V to 1.95-V V CC operation. The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable OE input is high. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree WCSP (DSBGA) Reel of 3000 SN74AUC1G125YZPR _UM_ 0.23-mm Large Bump YZP (Pb-free) SON DRY Reel of 5000 SN74AUC1G125DRYR PREVIEW C to C SOT (SOT-23) DBV Reel of 3000 SN74AUC1G125DBVR U25_ SOT (SC-70) DCK Reel of 3000 SN74AUC1G125DCKR UM_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. NanoFree is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains Copyright 2002 2007, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) A Y OE 1 2 4 Absolute Maximum Ratings (1) SN74AUC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES382K MARCH 2002 REVISED APRIL 2007 This device is fully specified for partial-power-down I off The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUT Y OE A L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 3.6 V V I Input voltage range (2) 0.5 3.6 V V O Voltage range applied to any output in the high-impedance or power-off state (2) 0.5 3.6 V V O Output voltage range (2) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through V CC or GND 100 mA DBV package 206 DCK package 252 θ JA Package thermal impedance (3) C/W DRY package 234 YZP package 132 T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback

www.ti.com Recommended Operating Conditions (1) SN74AUC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES382K MARCH 2002 REVISED APRIL 2007 MIN MAX UNIT V CC Supply voltage 0.8 2.7 V V CC 0.8 V V CC V IH High-level input voltage V CC 1.1 V to 1.95 V 0.65 V CC V V CC 2.3 V to 2.7 V 1.7 V CC 0.8 V V IL Low-level input voltage V CC 1.1 V to 1.95 V 0.35 V CC V V CC 2.3 V to 2.7 V 0.7 V I Input voltage 3.6 V V O Output voltage V CC V V CC 0.8 V 0.7 V CC 1.1 V I OH High-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V V CC 0.8 V 0.7 V CC 1.1 V I OL Low-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V V CC 0.8 V to 1.6 V Δ Δ v Input transition rise or fall rate V CC 1.65 V to 1.95 V ns/V V CC 2.3 V to 2.7 V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. Submit Documentation Feedback

www.ti.com Electrical Characteristics Switching Characteristics Switching Characteristics Operating Characteristics SN74AUC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES382K MARCH 2002 REVISED APRIL 2007 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH 100 µ A 0.8 V to 2.7 V V CC 0.1 I OH 0.7 mA 0.8 V 0.55 I OH mA 1.1 V 0.8 V OH V I OH mA 1.4 V I OH mA 1.65 V 1.2 I OH mA 2.3 V 1.8 I OL 100 µ A 0.8 V to 2.7 V 0.2 I OL 0.7 mA 0.8 V 0.25 I OL mA 1.1 V 0.3 V OL V I OL mA 1.4 V 0.4 I OL mA 1.65 V 0.45 I OL mA 2.3 V 0.6 I I A or OE input V I V CC or GND to 2.7 V µ A I off V I or V O 2.7 V µ A I OZ V O V CC or GND 2.7 V µ A I CC V I V CC or GND, I O 0.8 V to 2.7 V µ A C I V I V CC or GND 2.5 V 2.5 pF C o V O V CC or GND 2.5 V 5.5 pF (1) All typical values are at T A over recommended operating free-air temperature range, C L pF (unless otherwise noted) (see Figure V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 0.8 V FROM TO 0.1 V 0.1 V 0.15 V 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX t pd A Y 4.7 0.8 3.6 0.4 2.3 0.6 1.5 0.5 1.3 ns t en OE Y 5.4 0.7 4.1 0.5 2.6 0.6 1.1 1.8 0.5 1.4 ns t dis OE Y 4.8 1.4 4.3 1.4 1.5 2.2 2.9 0.9 2.2 ns over recommended operating free-air temperature range, C L pF (unless otherwise noted) (see Figure V CC 1.8 V V CC 2.5 V FROM TO 0.15 V 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX t pd A Y 0.7 1.5 2.5 0.9 1.7 ns t en OE Y 1.6 2.6 1.1 1.9 ns t dis OE Y 1.8 2.2 3.1 0.8 1.7 ns T A C V CC 0.8 V V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V TEST PARAMETER UNIT CONDITIONS TYP TYP TYP TYP TYP Outputs Power enabled C pd dissipation f MHz pF Outputs capacitance 1.5 1.5 1.5 2.5 disabled Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION NOTES: A. C includes□probe□and□jig□capacitance. B. Waveform□1□is□for□an□output□with□internal□conditions□such□that□the□output□is□low,□except□when□disabled□by□the□output□control. Waveform□2□is□for□an□output□with□internal□conditions□such□that□the□output□is□high,□except□when□disabled□by□the□output□control. C. All□input□pulses□are□supplied□by□generators□having□the□following□characteristics:□PRR 10□MHz,□Z =□50 , slew□rate 1□V/ns. D. The□outputs□are□measured□one□at□a□time,□with□one□transition□per□measurement. E. t and□t are□the□same□as□t . F. t and□t are□the□same□as□t . G. t and□t are□the□same□as□t . L O PLZ PHZ dis PZL PZH en PLH PHL pd /c163 /c87 /c179 From□Output Under□Test C (see□Note A) L LOAD□CIRCUIT 2□×□VCC Open GND RL RL t /tPLH PHL Open TEST S1 2□×□VCCt /tPLZ PZL GNDt /tPHZ PZH 0□V tW Input 0□V Input Output Output VOLTAGE□WAVEFORMS PROPAGATION□DELAY TIMES INVERTING AND□NONINVERTING□OUTPUTS VOLTAGE□WAVEFORMS PULSE□DURATION VCC/2 VCC/2 VCC/2 VCC/2 VOL VOH VCC VCC VOH VOL VCC/2 VCC/2 VCC/2 VCC/2 tPLH tPHL tPLHtPHL thtsu Data□Input Timing□Input 0□V 0□V Output Waveform□1 (see□Note□B) CC Output Waveform□2 S1□at□GND (see□Note□B) VOL VOH 0□V /c1870□V Output Control VCC/2 VCC/2 V CC/2 VCC/2 VCC/2 VOLTAGE□WAVEFORMS ENABLE AND□DISABLE□TIMES LOW- AND□HIGH-LEVEL ENABLING VOLTAGE□WAVEFORMS SETUP AND□HOLD□TIMES VCC VCC VCC VCC/2 VCC/2 VCC tPZL tPLZ tPHZtPZH V – VOH /c68 V +□VOL /c68 0.8□V 1.2□V 0.1□V/c177 1.5□V 0.1□V/c177 1.8□V 0.15□V/c177 2.5□V 0.2□V/c177 1.8□V 0.15□V/c177 2.5□V 0.2□V/c177 VCC 2□k/c87 2□k/c87 2□k/c87 2□k/c87 2□k/c87 1□k/c87 500 /c87 RL 0.1□V 0.1□V 0.1□V 0.15□V 0.15□V 0.15□V 0.15□V V/c68 CL 15□pF 15□pF 15□pF 15□pF 15□pF 30□pF 30□pF SN74AUC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES382K MARCH 2002 REVISED APRIL 2007 Figure Load Circuit and Voltage Waveforms Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AUC1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUC1G125DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUC1G125DCKRG4 ACTIVE SC70 DCK 5 3000 TBD Call TI Call TI SN74AUC1G125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G125DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC1G125YZTR ACTIVE DSBGA YZT 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 3-May-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74AUC1G125DBVR DBV 5 HNT 180 9 3.23 3.17 1.37 4 8 Q3 SN74AUC1G125YZTR YZT 5 ASEK 180 8 1.1 1.6 0.7 4 8 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74AUC1G125DBVR DBV 5 HNT 200.0 200.0 30.0 SN74AUC1G125YZTR YZT 5 ASEK 220.0 220.0 34.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2007 Pack Materials-Page 2

.88 mm 1.38 mm 30 µm 30 µm

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