74AUC16374DGGRE4

SN74AUC16374 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

www.ti.com

FEATURES

(TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 V CC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 V CC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1CLK 1D1 1D2 GND 1D3 1D4 V CC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 V CC 2D5 2D6 GND 2D7 2D8 2CLK A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state (high or SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 Member of the Texas Instruments Widebus Family Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation I off Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max t pd of ns at 1.8 V Low Power Consumption, 20- µ A Max I CC 8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V CC but is designed specifically for 1.65-V to 1.95-V V CC operation. The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP DGG Tape and reel SN74AUC16374DGGR AUC16374 C to C TVSOP DGV Tape and reel SN74AUC16374DGVR MH374 VFBGA GQL (2) Tape and reel SN74AUC16374GQLR MH374 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) Package preview Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2002 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2 3 4 5 6 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels 132C1 Pin numbers shown are for the DGG and DGV packages. SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down I off The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. TERMINAL ASSIGNMENTS (1) A OE NC NC NC NC 1CLK B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 V CC V CC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 V CC V CC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K OE NC NC NC NC 2CLK (1) NC No internal connection FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OUTPUT Q OE CLK D L H H L L L L H or L X Q H X X Z LOGIC DIAGRAM (POSITIVE LOGIC)

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 3.6 V V I Input voltage range (2) 0.5 3.6 V V O Voltage range applied to any output in the high-impedance or power-off state (2) 0.5 3.6 V V O Output voltage range (2) 0.5 V CC 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through V CC or GND 100 mA DGG package θ JA Package thermal impedance (3) DGV package C/W GQL package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 0.8 2.7 V V CC 0.8 V V CC V IH High-level input voltage V CC 1.1 V to 1.95 V 0.65 V CC V V CC 2.3 V to 2.7 V 1.7 V CC 0.8 V V IL Low-level input voltage V CC 1.1 V to 1.95 V 0.35 V CC V V CC 2.3 V to 2.7 V 0.7 V I Input voltage 3.6 V V O Output voltage V CC V V CC 0.8 V 0.7 V CC 1.1 V I OH High-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V V CC 0.8 V 0.7 V CC 1.1 V I OL Low-level output current V CC 1.4 V mA V CC 1.65 V V CC 2.3 V Δ Δ v Input transition rise or fall rate ns/V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com Electrical Characteristics Timing Requirements Switching Characteristics SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH 100 µ A 0.8 V to 2.7 V V CC 0.1 I OH 0.7 mA 0.8 V 0.55 I OH mA 1.1 V 0.8 V OH V I OH mA 1.4 V I OH mA 1.65 V 1.2 I OH mA 2.3 V 1.8 I OL 100 µ A 0.8 V to 2.7 V 0.2 I OL 0.7 mA 0.8 V 0.25 I OL mA 1.1 V 0.3 V OL V I OL mA 1.4 V 0.4 I OL mA 1.65 V 0.45 I OL mA 2.3 V 0.6 I I All inputs V I V CC or GND to 2.7 V µ A I off V I or V O 2.7 V µ A I OZ V O V CC or GND 2.7 V µ A I CC V I V CC or GND, I O 0.8 V to 2.7 V µ A C i V I V CC or GND 2.5 V pF C o V O V CC or GND 2.5 V pF (1) All typical values are at T A over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 0.8 V 0.1 V 0.1 V 0.15 V 0.2 V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX f clock Clock frequency 250 250 250 250 MHz t w Pulse duration, CLK high or low 5.9 1.9 1.9 1.9 1.9 ns t su Setup time, data before CLK 1.4 1.2 0.7 0.6 0.6 ns t h Hold time, data after CLK 0.1 0.4 0.4 0.4 0.4 ns over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V V CC 0.8 V FROM TO 0.1 V 0.1 V 0.15 V 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX f max 250 250 250 250 MHz t pd CLK Q 7.3 4.5 0.8 2.9 0.7 1.5 2.8 0.7 2.2 ns t en OE Q 1.2 5.3 0.8 3.6 0.8 1.5 2.9 0.7 2.2 ns t dis OE Q 8.2 7.1 4.8 1.4 2.7 4.5 0.5 2.2 ns

www.ti.com Operating Characteristics (1) SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 T A C V CC 0.8 V V CC 1.2 V V CC 1.5 V V CC 1.8 V V CC 2.5 V TEST PARAMETER UNIT CONDITIONS TYP TYP TYP TYP TYP f data MHz, Outputs C pd Power f clk MHz, enabled, (each dissipation f out MHz, 24.1 26.2 31.2 pF output output) (2) capacitance OE GND, switching C L pF Outputs f data MHz, disabled, f clk MHz, Power clock f out not C pd(Z) dissipation 7.5 7.5 9.4 13.2 pF and switching, capacitance data OE V CC switching C L pF f data MHz, Outputs f clk MHz, C pd Power disabled, f out not (each dissipation clock 13.8 13.8 14.7 17.5 pF switching, clock) (3) capacitance only OE V CC switching C L pF (1) Total device C pd for multiple (n) outputs switching and (y) clocks inputs switching C pd (each output)} C pd (each clock)} (2) C pd (each output) is the C pd for each data bit (input and output circuitry) as it operates at MHz (Note: the clock is operating at MHz in this test, but its I CC component has been subtracted out). (3) C pd (each clock) is the C pd for the clock circuitry only as it operates at MHz.

www.ti.com PARAMETER MEASUREMENT INFORMATION VCC/2 thtsu From Output Under Test CL (see Note A) LOAD CIRCUIT 2 × VCC Open GND RL RL Data Input Timing Input VCC 0 V VCC

0 V0 V

INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION tPLH tPHL tPHL tPLH VOH VOH VOL VOL VCC 0 V Input Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VCC 0 V VOL + VΔ VOH − VΔ ≈ 0 V VCC VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Output Control VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC VCC/2 VCC/2 0.8 V 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω VCC RL 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V VΔ CL 15 pF 15 pF 15 pF 30 pF 30 pF SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403D JULY 2002 REVISED JUNE 2005 Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AUC16374DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUC16374DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC16374DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC16374DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC16374GQLR ACTIVE VFBGA GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74AUC16374ZQLR ACTIVE VFBGA ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2005 Addendum-Page 1

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2005, Texas Instruments Incorporated