74AS373

SN54ALS373A_16 TI1 | Alldatasheet

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SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Eight Latches in a Single Package /C0068 3-State Bus-Driving True Outputs /C0068 Full Parallel Access for Loading /C0068 Buffered Control Inputs /C0068 pnp Inputs Reduce dc Loading on Data Lines

description

These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE ) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OE GND V CC LE SN54ALS373A, ...J O R W PACKAGE SN54AS373 ...J PACKAGE SN74ALS373A, SN74AS373 ...D W , N , O R N S PACKAGE (TOP VIEW) 32 1 2 0 1 9 91 0 1 1 1 2 1 3 SN54ALS373A, SN54AS373 . . . FK PACKAGE (TOP VIEW)1D OE 5D 8Q GND LE VCC On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube SN74ALS373AN SN74ALS373AN PDIP – N Tube SN74AS373N SN74AS373N Tube SN74ALS373ADW ALS373A 0°Ct o7 0°C SOIC DW Tape and reel SN74ALS373ADWR ALS373A 0°C to 70°C SOIC – DW Tube SN74AS373DW AS373 Tape and reel SN74AS373DWR AS373 SOP NS Tape and reel SN74ALS373ANSR ALS373A SOP – NS Tape and reel SN74AS373NSR 74AS373 CDIP J Tube SNJ54ALS373AJ SNJ54ALS373AJ CDIP – J Tube SNJ54AS373J SNJ54AS373J –55°C to 125°C CFP – W Tube SNJ54ALS373AW SNJ54ALS373AW LCCC FK Tube SNJ54ALS373AFK SNJ54ALS373AFK LCCC – FK Tube SNJ54AS373FK SNJ54AS373FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L HL L L LX Q 0 H X X Z logic diagram (positive logic) OE LE To Seven Other Channels

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (SN54ALS373A, SN74ALS373A) (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54ALS373A SN74ALS373A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA TA Operating free-air temperature –55 125 0 70 °C timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ALS373A SN74ALS373A UNIT MIN MAX MIN MAX UNIT fclock Clock frequency MHz tw Pulse duration, LE high 12 10 ns tsu Setup time, data before LE↓ 10 10 ns th Hold time, data after LE↓ 7 7 ns

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS373A SN74ALS373A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VCC = 4.5 V to 5.5 V,IOH = –0.4 mA VCC –2 VCC –2 VOH VCC =45V IOH = –1 mA 2.4 3.3 V VCC = 4.5 V IOH = –2.6 mA 2.4 3.2 VOL VCC =45V IOL = 12 mA 0.25 0.4 0.25 0.4 VVOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V 20 20 µA IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA Outputs high 9 16 9 16 ICC VCC = 5.5 V Outputs low 16 25 16 25 mA Outputs disabled 17 27 17 27 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX§ UNIT SN54ALS373A SN74ALS373A MIN MAX MIN MAX tPLH D Q 2 17 2 12 ns tPHL D Q 1 19 4 16 ns tPLH LE AQ 6 29 6 22 ns tPHL LE Any Q 1 27 7 23 ns tPZH OE AQ 6 22 1 18 ns tPZL OE Any Q 5 24 5 20 ns tPHZ OE Any Q 2 16 1 10 ns tPLZ OE Any Q 2 24 2 12 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (SN54AS373, SN74AS373) (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54AS373 SN74AS373 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current 32 48 mA TA Operating free-air temperature –55 125 0 70 °C timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54AS373 SN74AS373 UNIT MIN MAX MIN MAX UNIT fclock Clock frequency MHz tw Pulse duration, LE high 5.5* 4.5* ns tsu Setup time, data before LE↓ 2* 2* ns th Hold time, data after LE↓ 3* 3* ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS373 SN74AS373 UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V,IOH = –2 mA VCC –2 VCC –2 VOH VCC =45V IOH = –12 mA 2.4 3.2 V VCC = 4.5 V IOH = –15 mA 2.4 3.3 VOL VCC =45V IOL = 32 mA 0.27 0.5 VVOL VCC = 4.5 V IOL = 48 mA 0.32 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA IOZL VCC = 5.5 V, VO = 0.4 V –50 –50 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IO ‡ VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA Outputs high 55 90 55 90 ICC VCC = 5.5 V Outputs low 55 85 55 85 mA Outputs disabled 65 100 65 100 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX§ UNIT SN54AS373 SN74AS373 MIN MAX MIN MAX tPLH D Q 3 9 3.5 6 ns tPHL D Q 3 8 3.5 6 ns tPLH LE AQ 6.5 14.5 6.5 11.5 ns tPHL LE Any Q 5 9 5 7.5 ns tPZH OE AQ 2 7.5 2 6.5 ns tPZL OE Any Q 4.5 10.5 4.5 9.5 ns tPHZ OE Any Q 3 10 3 6.5 ns tPLZ OE Any Q 3 8 3 7 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms

www.ti.com 17-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 83020012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83020012A SNJ54ALS 373AFK 8302001RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8302001RA SNJ54ALS373AJ JM38510/37203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37203B2A JM38510/37203BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 37203BRA M38510/37203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37203B2A M38510/37203BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 37203BRA SN54ALS373AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54ALS373AJ SN74ALS373ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI 0 to 70 SN74ALS373ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 G373A SN74ALS373ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A SN74ALS373ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A SN74ALS373ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A SN74ALS373ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A SN74ALS373AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS373AN SN74ALS373AN3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SN74ALS373ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A SN74ALS373ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS373A

www.ti.com 17-Dec-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74AS373DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS373 SN74AS373DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74AS373DWRE4 OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74AS373DWRG4 OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74AS373N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS373N SN74AS373N3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SN74AS373NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74AS373 SNJ54ALS373AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83020012A SNJ54ALS 373AFK SNJ54ALS373AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8302001RA SNJ54ALS373AJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 17-Dec-2015 Addendum-Page 3 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 :

• Catalog: SN74ALS373A , SN74AS373
• Military: SN54ALS373A , SN54AS373 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS373ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74ALS373ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS373ANSR SO NS 20 2000 367.0 367.0 45.0 SN74AS373NSR SO NS 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT (9.3)

0.07 MAX

0.07 MIN

20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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