74ALS563A PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 74ALS563A/74ALS564A Latch flip/flop Product specification IC05 Data Handbook
1996 Jul 01
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop 74ALS563A Octal transparent latch, inverting (3-State) 74ALS564A Octal D flip-flop, inverting (3-State)
21996 Jul 01 853–1306 01670
FEATURES
- 74ALS563A is broadside pinout and inverting version of 74ALS373
- 74ALS564A is broadside pinout and inverting version of 74ALS374
- Inputs and outputs on opposite side of package allow easy interface to microprocessors
- Useful as an input or output port for microprocessors
- 3-State outputs for bus interfacing
- Common output enable
- 74ALS573A and 74ALS574A are non-inverting version of 74ALS563B and 74ALS564A respectively TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74ALS563A 6.0ns 12mA 74ALS564A 6.0ns 15mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP74ALS563AN, 74ALS564AN SOT146-1 20-pin plastic SOL74ALS563AD, 74ALS564AD SOT163-1
DESCRIPTION
The 74ALS563A is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 74ALS563A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the inverted data that is present one setup time before the High-to-Low enable transition. The 74ALS564A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The active-Low output enable (OE ) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA E (74ALS563A) Enable input 1.0/1.0 20µA/0.1mA OE Output enable input (active-Low) 1.0/1.0 20µA/0.1mA CP (74ALS564A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA Q 0 – Q7 Data outputs 130/240 2.6mA/24mA NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 3
PIN CONFIGURATION – 74ALS563A 10 11 20OE GND VCC E SC00111 Q 0D0 D1 Q 1 D2 Q 2 Q 3D3 Q 4D4 Q 5D5 Q 6D6 Q 7D7 PIN CONFIGURATION – 74ALS564A 10 11 20OE GND VCC CP SF01052 Q 0D0 D1 Q 1 D2 Q 2 Q 3D3 Q 4D4 Q 5D5 Q 6D6 Q 7D7 LOGIC SYMBOL – 74ALS563A 345678 141516171819 11 E OE D0 D1 Q2 Q3 1213 SC00112 VCC =Pin 20 GND=Pin 10 LOGIC SYMBOL – 74ALS564A 345678 141516171819 11 CP OE D0 D1 Q2 Q3 1213 SF01053 VCC =Pin 20 GND=Pin 10 IEC/IEEE SYMBOL – 74ALS563A EN1 SC00113 EN2 IEC/IEEE SYMBOL – 74ALS564A EN1 SF01054
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 4
LOGIC DIAGRAM – 74ALS563A VCC = Pin 20 GND = Pin 10 D E Q Q 0 D E Q Q 1 D E Q Q 2 D E Q Q 3 D E Q Q 4 D E Q Q 5 D E Q Q 6 D E Q Q 7 11E SC00116 OE FUNCTION TABLE – 74ALS563A INPUTS OUTPUTS INTERNAL OPERATING MODE OE E Dn REGISTER Q 0 – Q7 OPERATING MODE L H L L H Enable and read register L H H H L Enable and read register L ↓ l L H Latch and read register L ↓ h H L Latch and read register L L X NC NC Hold H L X NC Z Disable outputs H H Dn Dn Z Disable outputs H = High voltage level h = High state must be present one setup time before the High-to-Low enable transition L = Low voltage level l = Low state must be present one setup time before the High-to-Low enable transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low enable transition
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 5
LOGIC DIAGRAM – 74ALS564A VCC = Pin 20 D CP Q Q 0 D CP Q Q 1 D CP Q Q 2 D CP Q Q 3 D CP Q Q 4 D CP Q Q 5 D CP Q Q 6 D CP Q Q 7 OE CP GND = Pin 10 SC00117 FUNCTION TABLE – 74ALS564A INPUTS OUTPUTS INTERNAL OPERATING MODE OE CP Dn REGISTER Q 0 – Q7 OPERATING MODE L ↑ l L H Load and read register L ↑ h H L Load and read register L ↑ X NC NC Hold H ↑ X NC Z Disable outputs H ↑ Dn Dn Z Disable outputs H = High voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time before the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition = Not Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 6
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –2.6 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 0 +70 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VO High level output voltage VCC = ±10%, VIL = MAX, IOH = –0.4mA VCC – 2 V VOH High-level output voltage CC , IL , VIH = MIN IOH = MAX 2.4 3.2 V VO Low level output voltage VCC = MIN, VIL = MAX, IOL = 12mA 0.25 0.40 V VOL Low-level output voltage CC , IL , VIH = MIN IOL = 24mA 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.5 V II Input current at maximum input voltageVCC = MAX, VI = 7.0V 0.1 mA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA I Low-level input 74ALS563A VCC = MAX V =04 V –0.1 mA IIL current 74ALS564A VCC = MAX , VI = 0.4V –0.2 mA IOZH Off-state output current, High-level voltage applied VCC = MAX, VI = 2.7V 20 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VI = 0.4V –20 µA IO Output current3 VCC = MAX, VO = 2.25V –30 –112 mA ICCH 7 12 mA 74ALS563A ICCL VCC = MAX 13 21 mA ICC Supply current (total) ICCZ 15 24 mA ICC Supply current (total) ICCH 11 18 mA 74ALS564A ICCL VCC = MAX 17 27 mA ICCZ 18 28 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS .
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 7
AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF, RL = 500Ω UNIT MIN MAX tPLH tPHL Propagation delay Dn to Qn Waveform 3 2.0 3.0 10.0 10.0 ns tPLH tPHL Propagation delay E to Q n 74ALS563A Waveform 2 4.0 4.0 13.0 13.0 ns tPZH tPZL Output enable time to High or Low level 74ALS563A Waveform 6 Waveform 7 1.0 3.0 9.0 11.0 ns tPHZ tPLZ Output disable time from High or Low level Waveform 6 Waveform 7 1.0 2.0 9.0 11.0 ns fMAX Maximum clock frequency Waveform 1 45 MHz tPLH tPHL Propagation delay CP to Q n Waveform 1 3.0 4.0 12.0 12.0 ns tPZH tPZL Output enable time to High or Low level 74ALS564A Waveform 6 Waveform 7 1.0 3.0 9.0 11.0 ns tPHZ tPLZ Output disable time from High or Low level Waveform 6 Waveform 7 1.0 2.0 9.0 11.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF, RL = 500Ω UNIT MIN MAX tsu(H) tsu(L) Setup time, High or Low Dn to E Waveform 4 6.0 6.0 ns th(H) th(L) Hold time, High or Low Dn to E 74ALS563A Waveform 4 6.0 6.0 ns tw (H) E Pulse width, High Waveform 1 10.0 ns tsu(H) tsu(L) Setup time, High or Low Dn to CP Waveform 5 6.0 6.0 ns th(H) th(L) Hold time, High or Low Dn to CP 74ALS564A Waveform 5 1.0 1.0 ns tw (H) tw (L) CP Pulse width, High or Low Waveform 5 7.0 11.0 ns
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 8
For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. CP VM VMVM tw (H) 1/fmax VMVM tPHLtw (L)tPLH Qn SF00258 Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Widths, and Maximum Clock Frequency tPHL EV M VMVM tw (H) VMVMQ n tPLH SF00259 Waveform 2. Propagation Delay for Enable to Output and Enable Pulse Width Dn VM VM VMVM tPHLtPLH Qn SF00260 Waveform 3. Propagation Delay for Data to Output VM VM VM VM VM VM tsu(L) t h(L)tsu(H) t h(H) E Dn SF00261 Waveform 4. Data Setup Time and Hold Times VM VM VM VM VM VM tsu(L) t h(L)tsu(H) t h(H) CP Dn SF00262 Waveform 5. Data Setup Time and Hold Times VM VM VM tPHZtPZH OE Qn, Qn VOH -0.3V SC00114 Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL OE Qn, Qn VOL +0.3V SC00115 3.5V Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Philips Semiconductors Product specification 74ALS563A/74ALS564ALatch/flip-flop
1996 Jul 01 9
TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) 0.3V 0.3V tTHL (tff) INPUT PULSE REQUIREMENTS Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns Input Pulse Definition VCC Family 74ALS D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) Amplitude 3.5V 1.3V VM SC00072 R L 7.0V SWITCH POSITION TEST SWITCH tPLZ , tPZL closed All other open
Philips Semiconductors Product specification Latch flip–flop
1996 Jul 01 10
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification Latch flip–flop
1996 Jul 01 11
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification Latch flip–flop
1996 Jul 01 12
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. /C0109 /C0110 /C0114