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SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D – APRIL 1982 – REVISED MARCH 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers /C0068 pnp Inputs Reduce dc Loading /C0068 Data Flowthrough Pinout (All Inputs on Opposite Side From Outputs)

description

These octal buffers and line drivers are designed to have the performance of the popular SN54ALS240A/SN74ALS240A series and, at the same time, offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state control gate is a 2-input NOR gate such that, if either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. The SN74ALS540 provides inverted data. The ’ALS541 provide true data at the outputs. The -1 versions of SN74ALS540 and SN74ALS541 are identical to the standard versions, except that the recommended maximum I OL is increased to 48 mA. There is no -1 version of the SN54ALS541. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SN54ALS541 ...J PACKAGE SN74ALS540 ...D W , N , O R N S PACKAGE SN74ALS541 . . . DB, DW, N, OR NS PACKAGE (TOP VIEW) SN54ALS541 . . . FK PACKAGE (TOP VIEW) OE1 GND V CC OE2 3212 0 1 9 91 0 1 1 1 2 1 3 OE1 Y6 OE2 GND VCC On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D – APRIL 1982 – REVISED MARCH 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SN74ALS540N SN74ALS540N PDIP N Tube SN74ALS540-1N SN74ALS540-1N PDIP – N Tube SN74ALS541N SN74ALS541N SN74ALS541-1N SN74ALS541-1N Tube SN74ALS540DW ALS540 Tape and reel SN74ALS540DWR ALS540 Tube SN74ALS540-1DW ALS540-1 SOIC – DW Tube SN74ALS541DW ALS541 0°C to 70°C Tape and reel SN74ALS541DWR ALS541 Tube SN74ALS541-1DW ALS541 1 Tape and reel SN74ALS541-1DWR ALS541 -1 Tape and reel SN74ALS540NSR ALS540 SOP NS SN74ALS540-1NSR ALS540-1 SOP – NS Tape and reel SN74ALS541NSR ALS541 SN74ALS541-1NSR ALS541-1 SSOP DB Tape and reel SN74ALS541DBR G541 SSOP – DB Tape and reel SN74ALS541-1DBR G541-1 55°Ct o1 2 5°C CDIP – J Tube SNJ54ALS541J SNJ54ALS541J –55°C to 125°C LCCC – FK Tube SNJ54ALS541FK SNJ54ALS541FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. logic diagrams (positive logic) OE1 OE2 A1 Y1 To Seven Other Channels SN74ALS540 ′ALS541 OE1 OE2 A1 Y1 To Seven Other Channels

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D – APRIL 1982 – REVISED MARCH 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54ALS541 SN74ALS540 SN74ALS541 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –12 –15 mA IOL Low level output current 12 24 mAIOL Low -level output current 48† mA TA Operating free-air temperature –55 125 0 70 °C † Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D – APRIL 1982 – REVISED MARCH 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS541 SN74ALS540 SN74ALS541 UNIT MIN TYP ‡ MAX MIN TYP ‡ MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V,IOH = –0.4 mA VCC –2 VCC –2 VOH IOH = –3 mA 2.4 3.2 2.4 3.2 VVOH VCC = 4.5 V IOH = –12 mA 2 V IOH = –15 mA 2 IOL = 12 mA 0.25 0.4 0.25 0.4 VOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V IOL = 48 mA† 0.35 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 20 20 µA IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.1 mA IO § VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA Outputs high 5 10 SN74ALS540 VCC = 5.5 V Outputs low 13 22 ICC Outputs disabled 11 19 mAICC Outputs high 6 14 6 14 mA ’ALS541 VCC = 5.5 V Outputs low 15 25 15 25 Outputs disabled 13.5 32 13.5 22 † Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX¶ UNIT SN54ALS541 SN74ALS540 SN74ALS541 MIN MAX MIN MAX MIN MAX tPLH A Y 4 17 2 12 4 14 ns tPHL A Y 2 14 2 9 2 10 ns tPZH OE Y 5 18 5 15 5 15 ns tPZL OE Y 8 28 8 20 8 20 ns tPHZ OE Y 1 12 1 10 1 10 ns tPLZ OE Y 2 14 2 12 2 12 ns ¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-89602012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-8960201RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC 5962-8960201SA OBSOLETE CFP W 20 TBD Call TI Call TI SN54ALS541J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC SN74ALS540-1DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540-1DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540-1DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74ALS540-1N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS540-1NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS540-1NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540-1NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS540N3 OBSOLETE PDIP N 20 TBD Call TI Call TI SN74ALS540NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS540NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS540NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74ALS541-1NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS541-1NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541-1NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS541N3 OBSOLETE PDIP N 20 TBD Call TI Call TI SN74ALS541NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS541NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS541NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ALS541FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54ALS541J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 3

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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Product Information

74ALS540 specifications and overview.

Summary

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

Description

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

Source title 74ALS540 Datasheet(PDF) - Texas Instruments

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