74AC11000_12 TI1 | Alldatasheet

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V CC VCC D OR N PACKAGE (TOP VIEW)

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V CC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) µ m Process 500-mA Typ Latch-Up Immunity at 125 C Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N) This device contains four independent 2-input NAND gates. It performs the Boolean function Y A B or Y A B in positive logic. The 74AC11000 is characterized for operation from C to FUNCTION TABLE (EACH GATE) INPUTS OUTPUT Y A B H H L L X H X L H LOGIC SYMBOL (1) (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. EPIC is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1987 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Absolute Maximum Ratings (1) 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054B APRIL 1987 REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 V V I Input voltage range (2) 0.5 V CC 0.5 V V O Output voltage range (2) 0.5 V CC 0.5 V I IK Input clamp current V I or V I V CC mA I OK Output clamp current V O or V O V CC mA I O Continuous output current V O to V CC mA Continuous current through V CC or GND 100 mA D package 1.3 Maximum power dissipation at T A C (in still air) (3) W N package 1.1 T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

www.ti.com Recommended Operating Conditions Electrical Characteristics 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054B APRIL 1987 REVISED JUNE 2005 MIN NOM MAX UNIT V CC Supply voltage 5.5 V V CC V 2.1 V IH High-level input voltage V CC 4.5 V 3.15 V V CC 5.5 V 3.85 V CC V 0.9 V IL Low-level input voltage V CC 4.5 V 1.35 V V CC 5.5 V 1.65 V I Input voltage V CC V V O Output voltage V CC V V CC V I OH High-level output current V CC 4.5 V mA V CC 5.5 V V CC V I OL Low-level output current V CC 4.5 V mA V CC 5.5 V Δ Δ v Input transition rise fall rate ns/V T A Operating free-air temperature C over recommended operating free-air temperature range (unless otherwise noted) T A C PARAMETER TEST CONDITIONS V CC MIN MAX UNIT MIN TYP MAX V 2.9 2.9 I OH µ A 4.5 V 4.4 4.4 5.5 V 5.4 5.4 V OH I OH mA V 2.58 2.48 V 4.5 V 3.94 3.8 I OH mA 5.5 V 4.94 4.8 I OH mA (1) 5.5 V 3.85 V 0.1 0.1 I OL µ A 4.5 V 0.1 0.1 5.5 V 0.1 0.1 V OL I OL mA V 0.36 0.44 V 4.5 V 0.36 0.44 I OL mA 5.5 V 0.36 0.44 I OL mA (1) 5.5 V 1.65 I I V I V CC or GND 5.5 V 0.1 µ A I CC V I V CC or GND, I O 5.5 V µ A C i V I V CC or GND V 3.5 pF (1) Not more than one output should be tested at a time, and the duration of the test should not exceed ms.

www.ti.com Switching Characteristics Switching Characteristics Operating Characteristics PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMSLOAD CIRCUIT Input (see Note B) 50% 50% VCC 50% VCC tPHL tPLH VCC Output VOL VOH 0 V From Output Under Test CL = 50 pF (see Note A) 500 Ω NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. 50% 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054B APRIL 1987 REVISED JUNE 2005 over recommended operating free-air temperature range, V CC 3.3 V 0.3 V (unless otherwise noted) (see Figure T A C FROM TO PARAMETER MIN MAX UNIT (INPUT) (OUTPUT) MIN TYP MAX t PLH 1.5 7.2 9.8 1.5 11.1 A or B Y ns t PHL 1.5 5.8 8.6 1.5 9.6 over recommended operating free-air temperature range, V CC V 0.5 V (unless otherwise noted) (see Figure T A C FROM TO PARAMETER MIN MAX UNIT (INPUT) (OUTPUT) MIN TYP MAX t PLH 1.5 6.5 1.5 7.4 A or B Y ns t PHL 1.5 4.4 6.1 1.5 6.8 V CC T A C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per gate C L pF, f MHz pF Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74AC11000D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 74AC11000NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 74AC11000NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AC11000NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 1

to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AC11000DR SOIC D 16 2500 333.2 345.9 28.6 74AC11000NSR SO NS 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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