74AC10 FAIRCHILD | Alldatasheet

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■ ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74AC10SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74AC10SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC10MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC10PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT10SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACT10PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Pin Names Description An, Bn, Cn Inputs O n Outputs

www.fairchildsemi.com 2 74AC10 • 74ACT10 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC . Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) −0.5V to VCC + 0.5V DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source or Sink Current (IO ) ± 50 mA DC V CC or Ground Current per Output Pin (ICC or IGND ) ± 50 mA Storage Temperature (TSTG ) −65°C to +150°C Junction Temperature (TJ) PDIP 140 °C Supply Voltage (VCC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I) 0V to V CC Output Voltage (VO ) 0V to V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (ΔV/Δt) AC Devices V IN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (ΔV/Δt) ACT Devices V IN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.5 2.75 3.85 3.85 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I OUT = −50 µA 5 . 55 . 4 95 . 4 5 . 4 VIN = VILor VIH 3.0 2.56 2.46 I OH = −12 mA 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 2) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I OUT = 50 µA 5.5 0.001 0.1 0.1 VIN = VIL or VIH 3.0 0.36 0.44 I OL = 12 mA 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 2) IIN Maximum Input 5.5 ±0.1 ±1.0 µA VI = VCC (Note 4) Leakage Current or GND IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 2.0 20.0 µA VIN = VCC (Note 4) Supply Current or GND

3 www.fairchildsemi.com 74AC10 • 74ACT10 Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI OUT = −50 µA Output Voltage 5.5 5.49 5.4 5.4 VIN = VILor VIH 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 5) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI OUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 5) IIN Maximum Input 5.5 ±0.1 ±1.0 µAV I = VCC , GND Leakage Current ICCT Maximum 5.5 0.6 1.5 mA V I = VCC − 2.1V ICC /Input IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 µA VIN = VCC Supply Current or GND Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units (V) C L = 50 pF C L = 50 pF (Note 7) Min Typ Max Min Max ns ns Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C Units (V) C L = 50 pF C L = 50 pF (Note 8) Min Typ Max Min Max Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pF V CC = OPEN C PD Power Dissipation Capacitance 25.0 pF V CC = 5.0V

www.fairchildsemi.com 4 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A

5 www.fairchildsemi.com 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com 6 74AC10 • 74ACT10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

7 www.fairchildsemi.com 74AC10 • 74ACT10 Triple 3-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com