74AC109

MC74AC109 ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6

1 Publication Order Number:

MC74AC109, MC74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high −speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs 1516 14 13 12 11 10 21 3 4567 VCC CD2 J2 K2 CP2 SD2 Q2 Q2 CD1 J1 K1 CP1 SD1 Q1 Q1 GND J1 K1 CP1 SD1 Q1 Q1 CD J K CP S D Q Q CD1

Figure 1. Pinout; 16−Lead Packages Conductors

ORDERING INFORMATION

MC74AC109N PDIP−16 25 Units/Rail MC74AC109D SOIC−16 48 Units/Rail MC74AC109DR2 2500 Tape & Reel TSSOP−16 DT SUFFIX CASE 948F MC74AC109DT TSSOP−16 96 Units/Rail MC74AC109DTR2 TSSOP−16 SOIC−16

2500 Tape & Reel

MC74ACT109N PDIP−16 25 Units/Rail MC74ACT109D SOIC−16 48 Units/Rail MC74ACT109DR2 2500 Tape & Reel MC74ACT109DT TSSOP−16 96 Units/Rail MC74ACT109DTR2 TSSOP−16 SOIC−16 See general marking information in the device marking section on page 6 of this data sheet. DEVICE MARKING INFORMATION EIAJ−16 M SUFFIX CASE 966 MC74AC109M EIAJ−16 MC74AC109MEL EIAJ−16 2000 Tape & Reel MC74ACT109M EIAJ−16 MC74ACT109MEL EIAJ−16 2000 Tape & Reel

50 Units/Rail

MC74AC109, MC74ACT109 http://onsemi.com RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit VCC Supply Voltage ′AC 2.0 5.0 6.0 V ′ACT 4.5 5.0 5.5 VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) 0 − VCC V tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − ns/V VCC @ 5.5 V − 25 − tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs VCC @ 4.5 V − 10 − ns/V TJ Junction Temperature (PDIP) − − 140 °C TA Operating Ambient Temperature Range −40 25 85 °C IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA 1. V IN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. V IN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC Unit Conditions TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits VIH Minimum High Level Input Voltage 5.5 2.75 3.85 3.85 VIL Maximum Low Level Input Voltage 5.5 2.75 1.65 1.65 VOH Minimum High Level Output Voltage 3.0 2.99 2.9 2.9 IOUT = −50 μA 4.5 4.49 4.4 4.4 V 5.5 5.49 5.4 5.4 V *VIN = VIL or VIH 3.0 − 2.56 2.46 −12 mA 4.5 − 3.86 3.76 IOH −24 mA 5.5 − 4.86 4.76 −24 mA VOL Maximum Low Level Output Voltage 3.0 0.002 0.1 0.1 IOUT = 50 μA 4.5 0.001 0.1 0.1 V 5.5 0.001 0.1 0.1 V *VIN = VIL or VIH 3.0 − 0.36 0.44 12 mA 4.5 − 0.36 0.44 IOL 24 mA 5.5 − 0.36 0.44 24 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 μA VI = VCC, GND IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max IOHD 5.5 − − −75 mA VOHD = 3.85 V Min ICC Maximum Quiescent Supply Current 5.5 − 4.0 40 μA VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: I IN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V CC.

MC74AC109, MC74ACT109 http://onsemi.com AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter VCC* (V) 74AC 74AC Unit Fig. No. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max fmax Maximum Clock Frequency 3.3 125 − − 100 − MHz 3−35.0 150 − − 125 − tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74AC 74AC Unit Fig. No. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Set−up Time, HIGH or LOW Jn or Kn to CPn 3.3 5.0 6.5 4.5 7.5 5.0 ns 3−9 th Hold Time, HIGH or LOW Jn or Kn to CPn 3.3 5.0 0.5 0.5 ns 3−9 tw Pulse Width CPn or CDn or SDn 3.3 5.0 4.0 3.5 4.5 3.5 ns 3−6 trec Recovery TIme CDn or SDn to CP 3.3 5.0 ns 3−9 *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT Unit Conditions TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 μA 5.5 5.49 5.4 5.4 *VIN = VIL or VIH 4.5 − 3.86 3.76 V IOH −24 mA 5.5 − 4.86 4.76 −24 mA *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time.

MC74AC109, MC74ACT109 http://onsemi.com DC CHARACTERISTICS (continued) Symbol ConditionsUnit 74ACT74ACT VCC (V) ParameterSymbol ConditionsUnit TA = −40°C to +85°C TA = +25°CVCC (V) ParameterSymbol ConditionsUnit Guaranteed LimitsTyp VCC (V) Parameter VOL Maximum Low Level Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 μA 5.5 0.001 0.1 0.1 *VIN = VIL or VIH 4.5 − 0.36 0.44 V IOL 24 mA 5.5 − 0.36 0.44 24 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 μA VI = VCC, GND IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max IOHD 5.5 − − −75 mA VOHD = 3.85 V Min ICC Maximum Quiescent Supply Current 5.5 − 4.0 40 μA VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter VCC* (V) 74ACT 74ACT Unit Fig. No. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max fmax Maximum Clock Frequency 5.0 145 − − 125 − MHz 3−3 tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn *Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT Unit Fig. No. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Set−up Time, HIGH or LOW Jn or Kn to CPn 5.0 − 2.0 2.5 ns 3−9 th Hold Time, HIGH or LOW Jn or Kn to CPn 5.0 − 2.0 2.0 ns 3−9 tw Pulse Width CPn or CDn or SDn 5.0 − 5.0 6.0 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC109, MC74ACT109 http://onsemi.com AC OPERATING REQUIREMENTS (continued) Symbol Fig. No.Unit 74ACT74ACT VCC* (V)ParameterSymbol Fig. No.Unit TA = −40°C to +85°C CL = 50 pF TA = +25°C CL = 50 pF VCC* (V)ParameterSymbol Fig. No.Unit Guaranteed MinimumTyp VCC* (V)Parameter trec Recovery TIme CDn or SDn to CP 5.0 − 0 0 ns 3−9 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 35 pF VCC = 5.0 V MARKING DIAGRAMS A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week AC109 AWLYWW MC74AC109N AWLYYWW AC 109 ALYW ACT109 AWLYWW ACT 109 ALYW MC74ACT109N AWLYYWW DIP−16 SO −16 TSSOP −16 EIAJ −16 74AC109 ALYW 74ACT109 ALYW

MC74AC109, MC74ACT109 http://onsemi.com PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− B F C S H G D J L M 16 PL SEATING 916 K PLANE−T− MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 /C0095/C0095/C0095/C0095 PDIP−16 N SUFFIX

16 PIN PLASTIC DIP PACKAGE

CASE 648−08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP−B−

−A− M0.25 (0.010) B S −T− D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 SO−16 D SUFFIX

16 PIN PLASTIC SOIC PACKAGE

CASE 751B−05 ISSUE J

MC74AC109, MC74ACT109 http://onsemi.com PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX

16 PIN PLASTIC TSSOP PACKAGE

CASE948F−01 ISSUE O ÇÇÇ ÇÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SECTION N−N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉÉ ÉÉÉ DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 16X REFK N N EIAJ−16 M SUFFIX

16 PIN PLASTIC EIAJ PACKAGE

CASE966−01 ISSUE O HE DIM MIN MAX MIN MAX INCHES MILLIMETERS 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 BSC 0.050 BSC 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 A HE LE /C009510 /C00950 /C009510 /C0095 LE /C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M L DETAIL P VIEW P c A b e 16 9 D Z E A b c D E e L M Z

MC74AC109, MC74ACT109 http://onsemi.com ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MC74AC109/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative