74AC109

74AC109 FAIRCHILD | Alldatasheet

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I ICC reduced by 50% I Outputs source/sink 24 mA I ACT109 has TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions FACT  is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC109PC N16E 16-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description J1, J2, K1, K2 Data Inputs CP 1, CP2 Clock Pulse Inputs C D1 , CD2 Direct Clear Inputs SD1 , SD2 Direct Set Inputs Q 1, Q2, Q1, Q2 Outputs

www.fairchildsemi.com 2 74AC109  74ACT109 Logic Symbols IEEE/IEC Truth Table (each half) H = HIGH Voltage Level L = LOW Voltage Level /c17 = LOW-to-HIGH Transition X = Immaterial Q 0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock Logic Diagram (one half shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs SD C D CP J K QQ LHX X X HL HLX X X LH LLX X X H H HH /c17 LL L H HH /c17 HL T o g g l e HH /c17 LHQ 0 Q 0 HH /c17 HH H L HHL X X Q 0 Q 0

3 www.fairchildsemi.com 74AC109  74ACT109 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation of FACT circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC . Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) −0.5V to VCC + 0.5V DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source or Sink Current (IO ) ± 50 mA DC V CC or Ground Current per Output Pin (ICC or IGND ) ± 50 mA Storage Temperature (TSTG ) −65°C to +150°C Junction Temperature (TJ) PDIP 140 °C Supply Voltage (VCC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I)0 V t o V CC Output Voltage (VO )0 V t o V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices V IN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ACT Devices V IN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.5 2.75 3.85 3.85 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I OUT = −50 µA 5.5 5.49 5.4 5.4 VIN = VIL or VIH 3.0 2.56 2.46 I OH = −12 mA 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 2) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I OUT = 50 µA 5.5 0.001 0.1 0.1 VIN = VIL or VIH 3.0 0.36 0.44 I OL = 12 mA 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 2) IIN Maximum Input 5.5 ± 0.1 ± 1.0 µA VI = VCC, (Note 4) Leakage Current GND IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 2.0 20.0 µA VIN = VCC (Note 4) Supply Current or GND

www.fairchildsemi.com 4 74AC109  74ACT109 Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI OUT = −50 µA Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 5) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI OUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 5) IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAF V I = VCC , GND ICCT Maximum ICC /Input 5.5 0.6 1.5 mA V I = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 2.0 20.0 µAV IN = VCC or GND Supply Current VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 7) Min Typ Max Min Max fMAX Maximum Clock 3.3 125 150 100 MHz Frequency 5.0 150 175 125 ns ns ns ns

5 www.fairchildsemi.com 74AC109  74ACT109 AC Operating Requirements for AC Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 8) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 3.3 3.5 6.5 7.5 ns Jn or Kn to CPn 5.0 2.0 4.5 5.0 tH Hold Time, HIGH or LOW 3.3 −1.5 0 0 ns Jn or Kn to CPn 5.0 −0.5 0.5 0.5 tW Pulse Width 3.3 2.0 7.0 7.5 ns C Dn or SDn 5.0 2.0 4.5 5.0 tREC Recovery Time 3.3 −2.5 0 0 ns C Dn or SDn to CPn 5.0 −1.5 0 0 VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 9) Min Typ Max Min Max fMAX Maximum Clock Frequency 5.0 145 210 125 MHz tPLH Propagation Delay CP n to Qn or Qn tPHL Propagation Delay CP n to Qn or Qn tPLH Propagation Delay C Dn or SDn to Qn or Qn tPHL Propagation Delay C Dn or SDn to Qn or Qn VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 10) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 0.5 2.0 2.5 ns Jn or Kn to CPn tH Hold Time, HIGH or LOW 5.0 0 2.0 2.0 ns Jn or Kn to CPn tW Pulse Width 5.0 3.0 5.0 6.0 ns CP n or CDn or SDn trec Recovery Time 5.0 −2.5 0 0 ns C Dn or SDn to CPn Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pF V CC = OPEN C PD Power Dissipation Capacitance 35.0 pF V CC = 5.0V

www.fairchildsemi.com 6 74AC109  74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

7 www.fairchildsemi.com 74AC109  74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 8 74AC109  74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

9 www.fairchildsemi.com 74AC109  74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com