74AC08 FAIRCHILD | Alldatasheet

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I ICC reduced by 50% on 74AC only I Outputs source/sink 24 mA Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in Tape and Reel.) Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions FACT /c165 is a trademark of Fairchild Semiconductor Corporation. Order Number Package Package DescriptionNumber 74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC08MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74AC08PC_NL (Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT08SCX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT08MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT08PC_NL (Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Description An, Bn Inputs O n Outputs

www.fairchildsemi.com 2 74AC08  74ACT08 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT /c165 circuits outside databook specifications. Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC . Supply Voltage (VCC ) /c16 0.5V to /c14 7.0V DC Input Diode Current (IIK) VI /c32 /c16 0.5V /c16 20 mA VI /c32 VCC /c14 0.5V /c14 20 mA DC Input Voltage (VI) /c16 0.5V to VCC /c14 0.5V DC Output Diode Current (IOK ) VO /c32 /c16 0.5V /c16 20 mA VO /c32 VCC /c14 0.5V /c14 20 mA DC Output Voltage (VO ) /c16 0.5V to VCC /c14 0.5V DC Output Source or Sink Current (IO ) /c114 50 mA DC V CC or Ground Current per Output Pin (ICC or IGND ) /c114 50 mA Storage Temperature (TSTG ) /c16 65/c113 C to /c14 150/c113 C Junction Temperature (TJ) PDIP 140 /c113 C Supply Voltage (VCC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I) 0V to V CC Output Voltage (VO ) 0V to V CC Operating Temperature (TA) /c16 40/c113 C to /c14 85/c113 C Minimum Input Edge Rate (/c39 V//c39 t) AC Devices V IN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (/c39 V//c39 t) ACT Devices V IN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA /c32 /c14 25/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Units Conditions (V) Typ Guaranteed Limits 5.5 2.75 3.85 3.85 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I OUT /c32 /c16 50 /c80 A 5.5 5.49 5.4 5.4 VIN /c32 VIL or VIH 3.0 2.56 2.46 I OH /c32 /c16 12 mA 4.5 3.86 3.76 V I OH /c32 /c16 24 mA 5.5 4.86 4.76 I OH /c32 /c16 24 mA (Note 3) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I OUT /c32 50 /c80 A 5.5 0.001 0.1 0.1 VIN /c32 VIL or VIH 3.0 0.36 0.44 I OL /c32 12 mA 4.5 0.36 0.44 V I OL /c32 24 mA 5.5 0.36 0.44 I OL /c32 24 mA (Note 3) IIN Maximum Input 5.5 /c114 0.1 /c114 1.0 /c80 AV I /c32 VCC , GND (Note 5) Leakage Current IOLD Minimum Dynamic 5.5 75 mA V OLD /c32 1.65V Max IOHD Output Current (Note 4) 5.5 /c16 75 mA V OHD /c32 3.85V Min ICC Maximum Quiescent 5.5 2.0 20.0 /c80 AV IN /c32 VCC (Note 5) Supply Current or GND

3 www.fairchildsemi.com 74AC08  74ACT08 Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time. Note 8: Voltage Range 3.3 is 3.3V /c114 0.3V Voltage Range 5.0 is 5.0V /c114 0.5V Note 9: Voltage Range 5.0 is 5.0V /c114 0.5V Capacitance Symbol Parameter VCC TA /c32 /c14 25/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT /c32 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT /c32 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI OUT /c32 /c16 50 /c80 A Output Voltage 5.5 5.49 5.4 5.4 VIN /c32 VIL or VIH 4.5 3.86 3.76 V IOH /c32 /c16 24 mA 5.5 4.86 4.76 I OH /c32 /c16 24 mA (Note 6) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI OUT /c32 50 /c80 A Output Voltage 5.5 0.001 0.1 0.1 VIN /c32 VIL or VIH 4.5 0.36 0.44 V IOL /c32 24 mA 5.5 0.36 0.44 I OL /c32 24 mA (Note 6) IIN Maximum Input Leakage Current 5.5 /c114 0.1 /c114 1.0 /c80 AV I /c32 VCC , GND ICCT Maximum ICC /Input 5.5 0.6 1.5 mA V I /c32 VCC /c16 2.1V IOLD Minimum Dynamic Output Current 5.5 75 mA V OLD /c32 1.65V Max IOHD (Note 7) 5.5 /c16 75 mA V OHD /c32 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 /c80 A VIN /c32 VCC Supply Current or GND VCC TA /c32 /c14 25/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Symbol Parameter (V) C L /c32 50 pF C L /c32 50 pF Units (Note 8) Min Typ Max Min Max ns ns VCC TA /c32 /c14 25/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Symbol Parameter (V) C L /c32 50 pF C L /c32 50 pF Units (Note 9) Min Typ Max Min Max Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pF V CC /c32 OPEN C PD Power Dissipation Capacitance 20.0 pF V CC /c32 5.0V

www.fairchildsemi.com 4 74AC08  74ACT08 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A

5 www.fairchildsemi.com 74AC08  74ACT08 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com 6 74AC08  74ACT08 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

7 www.fairchildsemi.com 74AC08  74ACT08 Quad 2-Input AND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com