74AC00SCX FAIRCHILD | Alldatasheet

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Technical content

Features

I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs General Description The AC00/ACT00 contains four, 2-input NAND gates.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Pin Description Logic Symbol IEEE/IEC Order Number Package Number Package Description 74AC00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Description A n , B n Inputs O n Outputs

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC00, 74ACT00 Rev. 1.4.1 2 74AC00, 74ACT00 — Quad 2-Input NAND Gate Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating V CC Supply Voltage –0.5V to +7.0V I IK DC Input Diode Current V I –0.5V –20mA V I V CC + 0.5 +20mA V I DC Input Voltage –0.5V to V CC + 0.5V I OK DC Output Diode Current V O –0.5V –20mA V O V CC + 0.5V +20mA V O DC Output Voltage –0.5V to V CC + 0.5V I O DC Output Source or Sink Current ±50mA I CC or I GND DC V CC or Ground Current per Output Pin ±50mA T STG Storage Temperature –65°C to +150°C T J Junction Temperature 140°C Symbol Parameter Rating V CC Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V V I Input Voltage 0V to V CC V O Output Voltage 0V to V CC T A Operating Temperature –40°C to +85°C V t Minimum Input Edge Rate, AC Devices: V IN from 30% to 70% of V CC V CC @ 3.3V, 4.5V, 5.5V 125mV/ns V t Minimum Input Edge Rate, ACT Devices: V IN from 0.8V to 2.0V, V CC @ 4.5V, 5.5V 125mV/ns

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC00, 74ACT00 Rev. 1.4.1 3 74AC00, 74ACT00 — Quad 2-Input NAND Gate Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC Symbol Parameter V CC (V) Conditions T A +25°C T A –40°C to +85°C UnitsTyp. Guaranteed Limits V IH Minimum HIGH Level Input Voltage 3.0 V OUT 0.1V or V CC – 0.1V 1.5 2.1 2.1 V 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 V IL Maximum LOW Level Input Voltage 3.0 V OUT 0.1V or V CC – 0.1V 1.5 0.9 0.9 V 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 V OH Minimum HIGH Level Output Voltage 3.0 I OUT –50µA 2.99 2.9 2.9 V 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 V IN V IL or V IH I OH –12mA 2.56 2.46 4.5 V IN V IL or V IH I OH –24mA 3.86 3.76 5.5 V IN V IL or V IH I OH –24mA (1) 4.86 4.76 V OL Maximum LOW Level Output Voltage 3.0 I OUT 50µA 0.002 0.1 0.1 V 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 V IN V IL or V IH I OL 12mA 0.36 0.44 4.5 V IN V IL or V IH I OL 24mA 0.36 0.44 5.5 V IN V IL or V IH I OL 24mA (1) 0.36 0.44 I IN (3) Maximum Input Leakage Current 5.5 V I V CC , GND ±0.1 ±1.0 µA I OLD Minimum Dynamic Output Current (2) 5.5 V OLD = 1.65V Max. 75 mA IOHD 5.5 V OHD = 3.85V Min. –75 mA ICC (3) Maximum Quiescent Supply Current 5.5 V IN = VCC or GND 2.0 20.0 µA

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC00, 74ACT00 Rev. 1.4.1 4 74AC00, 74ACT00 — Quad 2-Input NAND Gate Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. Symbol Parameter VCC (V) Conditions TA = +25°C T A = –40°C to +85°C UnitsTyp. Guaranteed Limits VIH Minimum HIGH Level Input Voltage 4.5 V OUT = 0.1V or VCC – 0.1V 1.5 2.0 2.0 V 5.5 1.5 2.0 2.0 VIL Maximum LOW Level Input Voltage 4.5 V OUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 V 5.5 1.5 0.8 0.8 VOH Minimum HIGH Level Output Voltage 4.5 I OUT = –50µA 4.49 4.4 4.4 V 5.5 5.49 5.4 5.4 4.5 V IN = VIL or VIH, IOH = –24mA 3.86 3.76

5.5 V IN = VIL or VIH,

IOH = –24mA(4) 4.86 4.76 VOL Maximum LOW Level Output Voltage 4.5 I OUT = 50µA 0.001 0.1 0.1 V 5.5 0.001 0.1 0.1 4.5 V IN = VIL or VIH, IOL = 24mA 0.36 0.44 IOL= 24mA(4) 0.36 0.44 IIN Maximum Input Leakage Current 5.5 V I = VCC, GND ±0.1 ±1.0 µA ICCT Maximum ICC/Input 5.5 V I = VCC – 2.1V 0.6 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 V OLD = 1.65V Max. 75 mA IOHD 5.5 V OHD = 3.85V Min. –75 mA ICC Maximum Quiescent Supply Current 5.5 V IN = VCC or GND 2.0 20.0 µA

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC00, 74ACT00 Rev. 1.4.1 5 74AC00, 74ACT00 — Quad 2-Input NAND Gate Note: Note: Capacitance Symbol Parameter V CC (V)(6) TA = +25°C, CL = 50pF TA = –40°C to +85°C, CL = 50pF Symbol Parameter V CC (V)(7) TA = +25°C, CL = 50pF TA = –40°C to +85°C, CL = 50pF Symbol Parameter Conditions Typ. Units CIN Input Capacitance V CC = OPEN 4.5 pF CPD Power Dissipation Capacitance V CC = 5.0V 30.0 pF

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow specifically the warranty therein, which covers Fairchild products. B) ALL DIMENSIONS ARE IN MILLIMETERS.

1.75 MAX

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide specifically the warranty therein, which covers Fairchild products.

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide specifically the warranty therein, which covers Fairchild products.

0.43 TYP

Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide specifically the warranty therein, which covers Fairchild products. B) ALL DIMENSIONS ARE IN MILLIMETERS. MOLD FLASH, AND TIE BAR EXTRUSIONS.

0.38 MIN

©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC00, 74ACT00 Rev. 1.4.1 10 TRADEMARKS Thef ollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK EZSWITCH™ * Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter®* FPS™ FRFET® Global Power Resource SM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® PDP-SPM™ Power220® Power247® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™ -3 SuperSOT™ -6 SuperSOT™ -8 SyncFET™ The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ *E Z S W ITCH™ and FlashWriter ® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHERDOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Form First Production ative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 74AC00, 74ACT00 — Quad 2-Input NAND Gate