CD74AC00 TI | Alldatasheet

Document overview

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Technical content

Features

  • Typical Propagation Delay - 3.2ns at VCC = 5V, TA = 25oC, CL = 50pF
  • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines

Description

The CD74AC00 and CD74ACT00 are quad 2-input NAND gates that utilize the Harris Advanced CMOS Logic technology. Pinout CD74AC00, CD74ACT00 (PDIP, SOIC) TOP VIEW Functional Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. CD74AC00E -55 to 125 14 Ld PDIP E14.3 CD74ACT00E -55 to 125 14 Ld PDIP E14.3 CD74AC00M -55 to 125 14 Ld SOIC M14.15 CD74ACT00M -55 to 125 14 Ld SOIC M14.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all elec- trical specifications. Please contact your local sales office or Harris customer service for ordering information. GND VCC TRUTH TABLE INPUTS OUTPUTS ABY LLH HLH LHH HHL GND = 7 V CC = 14 September 1998 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1998 CD74AC00, CD74ACT00 Quad 2-Input NAND Gate File Number 1855.1 [ /Title (CD74 AC00, CD74 ACT00 /Sub- ject (Quad 2-Input NAND Gate) /Autho r () /Key- words (Har- ris Semi- con- ductor, Advan ced CMOS , Harris Semi- con- ductor, Advan ced TTL) /Cre- ator ()

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC (Note 4) DC Input or Output Voltage, V Input Rise and Fall Slew Rate, dt/dv Thermal Resistance (Typical, Note 5) θ JA (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θ JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI(V) I O (mA) MIN MAX MIN MAX MIN MAX AC TYPES High Level Input Voltage V Low Level Input Voltage V IL - - 1.5 - 0.3 - 0.3 - 0.3 V -75 (Note 6, 7) -50 (Note 6, 7) CD74AC00, CD74ACT00

12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V (Note 6, 7) (Note 6, 7) 5 . 5 ----- 1.65 V Input Leakage Current I I VCC or GND Quiescent Supply Current, SSI ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA ACT TYPES High Level Input Voltage V IH - - 4.5 to 5.5 2-2-2-V Low Level Input Voltage V IL - - 4.5 to 5.5 24 4.5 - 0.36 - 0.44 - 0.5 V (Note 6, 7) (Note 6, 7) 5 . 5 ----- 1.65 V Input Leakage Current I I VCC or GND Quiescent Supply Current, SSI ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA Additional Supply Current per Input Pin TTL Inputs High

1 Unit Load

ΔI CC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD All 0.15 NOTE: Unit load isΔICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI(V) I O (mA) MIN MAX MIN MAX MIN MAX CD74AC00, CD74ACT00

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