74ABT16260 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 74ABT16260/74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) Product specification Supersedes data of 1996 Nov 20 IC23 Data Handbook

1998 Feb 10

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

21998 Feb 10 853-2048-18945

FEATURES

  • ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model (C = 200pF, R = 0).
  • Latch-up performance exceeds 500mA per JEDEC Standard JESD-17.
  • Distributed VCC and GND pin configuration minimizes high-speed switching noise.
  • Flow-through architecture optimizes PCB layout.
  • High-drive outputs (–32mA IOH , 64mA IOL ).
  • 74ABTH16260 incorporates bus-hold inputs which eliminate the need for external pull-up resistors.
  • Package options: – 56-pin plastic Shrink Small-Outline Package (SSOP) – 56-pin plastic Thin Shrink Small-Outline Package (TSSOP)

DESCRIPTION

The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in memory-interleaving applications. Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The output enable (OE1B OE2B , and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction. Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The 74ABTH incorporates the bus hold feature. The 74ABT does not include bus hold feature. Both parts are available in 56-pin SSOP and TSSOP. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH Propagation delay C =5 0pF 2.8 ns tPHL nAx to nBx nBx to nAx C L = 50 pF 2.5 ns C IN Input capacitance VI = 0 V or VCC 4 pF C OUT Output capacitance VI/O = 0 V or 5.0 V 6 pF ICCZ Total supply current Outputs disabled 100 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16260 DL BT16260 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16260 DGG BT16260 DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16260 DL BH16260 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16260 DGG BH16260 DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 An Data inputs/outputs (A) 23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 1Bn Data inputs/outputs (B1) 6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 2Bn Data inputs/outputs (B2) 1, 29, 56 OEA , OE1B, OE2B Output enable input (active low) 2, 27, 30, 55 LE1B, LE2B, LEA1B, LEA2B Latch enable inputs

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 3

V CC 2B8 2B7 2B9 GND 2B10A4 18 39 44A5 2B11 1B12 2B12 1B11 1B10 GND 19 38 GND A10 25 32 37A11 A12 VCC 1B1 1B2 1B9 V CC 1B8 1B6 1B5 GNDGND 26 31 1B41B3 27 30 LEA1BLE2B 28 29SEL OE1B LE1B 1B7 SA00435 FUNCTION TABLES B to A (OEB = H) INPUTS OUTPUT 1B 2B SEL LE1B LE2B OEA A H X H H X L H L X H H X L L X X H L X L A0 X H L X H L H X L L X H L L X X L X L L A0 X X X X X H Z A to B (OEA = H) INPUTS OUTPUT A LEA1B LEA2B OE1B OE2B 1B 2B H H H L L H H L H H L L L L H H L L L H 2B0 L H L L L L 2B0 H L H L L 1B0 H L L H L L 1B0 L X L L L L 1B0 2B0 X X X H H Z Z X X X L H Active Z X X X H L Z Active X X X L L Active Active

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 4

LOGIC DIAGRAM (POSITIVE LOGIC) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL 2B1 1B1 TO 11 OTHER CHANNELS SA00436

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 5

Over operating free-air temperature range (unless otherwise specified)1 SYMBOL PARAMETER CONDITIONS LIMITS UNITSYMBOL PARAMETER CONDITIONS MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range see Note 2 –0.5 7 V VO Voltage range applied to any output in the high state or power-off state –0.5 5.5 V IO Current into any output in the low state 128 mA IIK Input clamp current VI < 0 –18 mA IOK Output clamp current VO < 0 –50 mA Maximum power dissipation at Tamb = 55°C (in still air) see Note 3 1.4 W Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. RECOMMENDED OPERATING CONDITIONS 1 SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V IOH High-level output current –32 mA IOL Low-level output current 64 mA ΔtΔ/v Input transition rise or fall rate Outputs enabled 10 ns/V ΔtΔ/VCC Power-up ramp rate 200 µs/V Tamb Operating free-air temperature –40 +85 °C NOTE: 1. Unused or floating inputs must be held high or low.

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 6

DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85°C UNIT Min Typ Max Min Max VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.8 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VOH High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = VCC or GND Control pins ±0.01 ±1 ±1 µA I g VCC = 5.5V; VI = VCC or GND Data pins ±3 ±5 µA VCC = 4.5V; VI = 0.8V A or B 75 75 IHOLD Bus Hold current VCC = 4.5V; VI = 2.0V ports –75 –75 µA VCC = 5.5V; VI = 0 to 5.5V ±500 ±500 IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA IPU /IPD Power-up/down 3-State output current VCC = 2.0V; VO = 0.5V; VI = GND or VCC ; VOE = VCC ±60 ±200 ±200 µA IOZH 3-State output High currentVCC = 5.5V; VO = 2.7V; VI = VIL or VIH 1.0 10 10 µA IOZL 3-State output Low currentVCC = 5.5V; VO = 0.5V; VI = VIL or VIH –1.0 –10 –10 µA ICEX Output high leakage currentVCC = 5.5V; VO = 5.5V; VI = GND or VCC 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –100 –225 –50 –225 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.2 1.5 1.5 ICC Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 8 19 19 mAICC Quiescent su ly current VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.1 1.0 1.0 mA ΔICC Additional supply current per input pin2 Outputs enabled, one input at 3.4V, other inputs at V CC or GND; VCC = 5.5V 0.1 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V CC or GND. 3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state.

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 7

AC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) SYMBOL PARAMETER VCC = 5V, Tamb = 25°C Tamb = –40°C to +85°C UNITSYMBOL FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX UNIT tPLH Ao rB Bo rA 1 2.8 4.8 1 5.6 ns tPHL A or B B or A 1 2.5 5 1 5.9 ns tPLH LE Ao rB tPHL LE A or B t tPLH SEL (B2) A 1.1 2.8 4.9 1.1 6 ns t tPHL tPZH OE Ao rB 1 2.9 4.7 1 5.7 ns tPZL OE A or B tPHZ OE Ao rB tPLZ OE A or B AC SETUP CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted) SYMBOL PARAMETER VCC = 5V, Tamb = 25°C Tamb = –40°C to +85°C UNITSYMBOL PARAMETER MIN MAX MIN MAX UNIT tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 3.3 ns tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓ 1.5 1.5 ns th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓ 1 1 ns

1998 Feb 10 8

The outputs are measured one at a time with one transition per measurement. Figure 1. Pulse duration characteristics: PRR ≤ 10MHz, ZO = 50Ω , tr ≤ 2.5ns, tf ≤ 2.5ns. Figure 2. Propagation delay times; Figure 3. Setup and hold times output is low except when disabled by the output control. output is high except when disabled by the output control. Figure 4. Enable and disable times; Figure 5. Test load circuit

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 9

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 10

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 11

Philips Semiconductors Product specification 74ABT16260 74ABTH1626012-bit to 24-bit multiplexed D-type latches (3-State)

1998 Feb 10 12

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 05-96 Document order number: 9397-750-03339 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.