SN54ABT162500_08 TI1 | Alldatasheet
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SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Members of the Texas Instruments Widebus Family /C0068B-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required /C0068State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation /C0068UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode /C0068Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C /C0068High-Impedance State During Power Up and Power Down /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Latch-Up Performance Exceeds 500 mA Per JESD 17 /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Package Options Include Plastic Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA ), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. SN54ABT162500 ...W D PACKAGE SN74ABT162500 . . . DL PACKAGE (TOP VIEW) OEAB LEAB GND VCC GND A10 A11 A12 GND A13 A14 A15 V CC A16 A17 GND A18 OEBA LEBA GND CLKAB GND V CC GND B10 B11 B12 GND B13 B14 B15 V CC B16 B17 GND B18 CLKBA GND Copyright 1999, Texas Instruments IncorporatedUNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
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description (continued) When V CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT162500 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT162500 is characterized for operation from –40°C to 85°C. FUNCTION TABLE † INPUTS OUTPUT OEAB LEAB CLKAB A B L X X X Z H HX LL H HX HH H L ↓ LL H L ↓ HH H LH X B 0‡ H L L X B0§ † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA , LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic symbol† EN1 OEAB 2C3 A1 B1 A14 A15 A16 A17 A10 A11 A12 B13 B14 B15 B16 B17 B18 6D4 A18 B10 B11 B12 LEBA EN4 LEAB 5C6CLKBA OEBA CLKAB A13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
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logic diagram (positive logic) CLK CLK OEAB CLKAB LEAB LEBA CLKBA OEBA To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54ABT162500 SN74ABT162500 UNIT MIN MAX MIN MAX UNIT VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High level output current A port –24 –32 mAIOH High-level output current B port –12 –12 mA IOL Low level output current A port 48 64 mAIOL Low-level output current B port 12 12 mA Δt/Δv Input transition rise or fall rate Outputs enabled 10 10 ns/V Δt/ΔVCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C SN54ABT162500 SN74ABT162500 UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN MAX MIN MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 A port VCC = 5 V, IOH = –3 mA 3 3 3 A port VCC =45V IOH = –24 mA 2 2 VOH VCC = 4.5 V IOH = –32 mA 2* 2 VVOH VCC = 4.5 V, IOH = –1 mA 3.35 3.3 3.35 V B port VCC = 5 V, IOH = –1 mA 3.85 3.8 3.85 B port VCC =45V IOH = –3 mA 3.1 3 3.1 VCC = 4.5 V IOH = –12 mA 2.6 2.6 A port VCC =45V IOL = 48 mA 0.55 0.55 VOL A port VCC = 4.5 V IOL = 64 mA 0.55* 0.55 V B port VCC = 4.5 V, IOL = 12 mA 0.8 0.8 0.8 Vhys 100 mV Control inputsVCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 II A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20 ±20 ±20 µA IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE or OE = X§ ±50 ±50 ±50 µA IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE or OE = X§ ±50 ±50 ±50 µA IOZH ‡ VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V or OE ≤ 0.8 V 10 10 10 µA IOZL ‡ VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V or OE ≤ 0.8 V –10 –10 –10 µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA I ¶ A port VCC =55V VO =25V mAIO ¶ B port VCC = 5.5 V, VO = 2.5 V mA VCC = 5.5 V, Outputs high 3 3 3 ICC A or B ports VCC = 5.5 V, IO = 0, Outputs low 36 36 36 mA VI = VCC or GND Outputs disabled 3 3 3 ΔICC # VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 50 50 50 µA C i Control inputsVI = 2.5 V or 0.5 V 3 pF C io A or B ports VO = 2.5 V or 0.5 V 9 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT162500 SN74ABT162500 UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 150 150 MHz t Pulse duration LEAB or LEBA high 2.5 2.5 nstw Pulse duration CLKAB or CLKBA high or low 3 3 ns A before CLKAB↓ 3.3 3.3 t Setup time B before CLKBA↓ 3.3 3.3 nstsu Setup time A before LEAB↓ or B before LEBA↓ CLK high 1 1 ns A before LEAB ↓ or B before LEBA ↓ CLK low 2.5 2.5 th Hold time A after CLKAB↓ or B after CLKBA↓ 0 0 nsth Hold time A after LEAB↓ or B after LEBA↓ 2 2 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT162500 SN74ABT162500 UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 150 200 150 150 MHz tPLH Ao rB Bo rA ns tPHL A or B B or A 2 3.4 5.2 2 6.1 2 5.7 ns tPLH LEAB or LEBA Bo rA 2 3.3 4.8 2 6.1 2 5.6 ns tPHL LEAB or LEBA B or A 2 3.8 5.2 2 6.4 2 5.9 ns tPLH CLKAB or CLKBA Bo rA ns tPHL CLKAB or CLKBA B or A ns tPZH OEAB or OEBA Bo rA ns tPZL OEAB or OEBA B or A 2 3.8 4.7 2 5.6 2 5.4 ns tPHZ OEAB or OEBA Bo rA 2 4.5 5.7 2 6.9 2 6.5 ns tPLZ OEAB or OEBA B or A ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74ABT162500DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT162500DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT162500DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT162500DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT162500DLR SSOP DL 56 1000 346.0 346.0 49.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
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