74ABT16245 FAIRCHILD | Alldatasheet

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Features

I Bidirectional non-inverting buffers I Separate control logic for each byte I 16-bit version of the ABT245 I A and B output sink capability of 64 mA, source capability of 32 mA I Guaranteed output skew I Guaranteed multiple output switching specifications I Output switching specified for both 50 pF and 250 pF loads I Guaranteed simultaneous switching noise level and dynamic threshold performance I Guaranteed latchup protection I High impedance glitch free bus loading during entire power up and power down cycle I Non-destructive hot insertion capability Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram Order Number Package Number Package Description 74ABT16245CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74ABT16245CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OEn Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A15 Side A Inputs/Outputs B0–B15 Side B Inputs/Outputs

www.fairchildsemi.com 2 74ABT16245 Truth Tables H /c32 HIGH Voltage Level L /c32 LOW Voltage Level X /c32 Immaterial Z /c32 High Impedance Functional Description The ABT16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagrams Inputs Outputs OE1 T/R1 L L Bus B 0–B7 Data to Bus A0–A7 L H Bus A 0–A7 Data to Bus B0–B7 H X HIGH-Z State on A 0–A7, B0–B 7 Inputs Outputs OE2 T/R2 L L Bus B 8–B15 Data to Bus A8–A 15 L H Bus A 8–A15 Data to Bus B8–B 15 H X HIGH-Z State on A 8–A15, B8–B 15

3 www.fairchildsemi.com 74ABT16245 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Note 3: Guaranteed, but not tested. Storage Temperature /c16 65/c113 C to /c14 150/c113 C Ambient Temperature under Bias /c16 55/c113 C to /c14 125/c113 C Junction Temperature under Bias /c16 55/c113 C to /c14 150/c113 C VCC Pin Potential to Ground Pin /c16 0.5V to /c14 7.0V Input Voltage (Note 2) /c16 0.5V to /c14 7.0V Input Current (Note 2) /c16 30 mA to /c14 5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State /c16 0.5V to 5.5V in the HIGH State /c16 0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current /c16 500 mA Over Voltage Latchup (I/O) 10V Free Air Ambient Temperature /c16 40/c113 C to /c14 85/c113 C Supply Voltage /c14 4.5V to /c14 5.5V Minimum Input Edge Rate (/c39 V//c39 t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage /c16 1.2 V Min I IN /c32 /c16 18 mA (OEn, T/Rn) VOH Output HIGH Voltage 2.5 V Min I OH /c32 /c16 3 mA (An, Bn)

2.0 V Min I OH /c32 /c16 32 mA (An, Bn)

VOL Output LOW Voltage 0.55 V Min I OL /c32 64 mA (An, Bn) IIH Input HIGH Current 1 /c80 AM a x V IN /c32 2.7V (OEn, T/Rn) (Note 3) 1V IN /c32 VCC (OEn, T/Rn) IBVI Input HIGH Current Breakdown Test 7 /c80 AM a x V IN /c32 7.0V (OEn, T/Rn) IBVIT Input HIGH Current Breakdown Test (I/O) 100 /c80 AM a x V IN /c32 5.5V (An, Bn) IIL Input LOW Current /c16 1 /c80 AM a x V IN /c32 0.5V (OEn, T/Rn) (Note 3) /c16 1V IN /c32 0.0V (OEn, T/Rn) VID Input Leakage Test 4.75 V 0.0 I ID /c32 1.9 /c80 A (OEn, T/Rn) All Other Pins Grounded IIH /c14 I OZH Output Leakage Current 10 /c80 A0 /c16 5.5V VOUT /c32 2.7V (An, Bn); OE /c32 2.0V IIL /c14 I OZL Output Leakage Current /c16 10 /c80 A0 /c16 5.5V VOUT /c32 0.5V (An, Bn); OE /c32 2.0V IOS Output Short-Circuit Current /c16 100 /c16 275 mA Max V OUT /c32 0.0V (An, Bn) ICEX Output HIGH Leakage Current 50 /c80 AM a x V OUT /c32 VCC (An, Bn) IZZ Bus Drainage Test 100 /c80 A0 . 0 V OUT /c32 5.50V (An, Bn); All Others GND ICCH Power Supply Current 100 /c80 A Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 100 /c80 AM a x O E n /c32 VCC , T/Rn /c32 GND or VCC All others at VCC or GND ICCT Additional ICC /Input Outputs Enabled 2.5 mA V I /c32 VCC /c16 2.1V Outputs 3-STATE 2.5 mA Max OE n, T/ Rn VI /c32 VCC /c16 2.1V Outputs 3-STATE 50 /c80 A Data Input V I /c32 VCC /c16 2.1V All others at VCC or GND ICCD Dynamic ICC No Load mA/ Max Outputs OPEN (Note 3) 0.1 MHz OE n /c32 GND, T/Rn /c32 GND or VCC One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 4 74ABT16245 DC Extended Electrical Characteristics Note 4: Max number of outputs defined as (n). n /c16 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of outputs defined as (n). n /c16 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 6: Max number of data inputs (n) switching. n /c16 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Extended AC Electrical Characteristics Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac- itors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: 3-STATE delay are dominated by the RC network (500/c58 , 250 pF) on the output and have been excluded from the datasheet. Symbol Parameter Min Typ Max Units VCC Conditions C L /c32 50 pF; RL /c32 500/c58 VOLP Quiet Output Maximum Dynamic VOL 0.5 0.9 V 5.0 T A /c32 25/c113 C (Note 4) VOLV Quiet Output Minimum Dynamic VOL /c16 1.4 /c16 1.0 V 5.0 T A /c32 25/c113 C (Note 4) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 T A /c32 25/c113 C (Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.4 V 5.0 T A /c32 25/c113 C (Note 5) VILD Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 T A /c32 25/c113 C (Note 6) Symbol Parameter TA /c32 /c14 25/c113 C T A /c32 /c16 55/c113 C to /c14 125/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C Units VCC /c32 /c14 5V V CC /c32 4.5V – 5.5V V CC /c32 4.5V – 5.5V C L /c32 50 pF C L /c32 50 pF C L /c32 50 pF Min Typ Max Min Max Min Max ns ns ns Symbol Parameter TA /c32/c16 40/c113 C to /c14 85/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C Units CL /c32 50 pF C L /c32 250 pF C L /c32 250 pF

16 Outputs Switching 1 Output Switching 16 Outputs Switching

(Note 7) (Note 8) (Note 9) Min Typ Max Min Max Min Max fTOGGLE Maximum Toggle Frequency 100 MHz ns ns tPHZ Output Disable 1.0 6.9 (Note 10) (Note 10) ns tPLZ Time 1.0 6.9

5 www.fairchildsemi.com 74ABT16245 Skew Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL ), LOW to HIGH (tOSLH ), or any combination switching LOW-to-HIGH and/or HIGH-to- LOW (tOST ). The specification is guaranteed but not tested. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC ) from device to device. This specification is guaranteed but not tested. Capacitance Note 16: C I/O is measured at frequency f /c32 1 MHz, per MIL-STD-883, Method 3012. Symbol Parameter TA /c32 /c16 40/c113 C to /c14 85/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C Units VCC /c32 4.5V–5.5V V CC /c32 4.5V–5.5V CL /c32 50 pF C L /c32 250 pF

16 Outputs Switching 16 Outputs Switching

(Note 11) (Note 12) Max Max tOSHL Pin to Pin Skew 1.3 1.5 ns (Note 13) HL Transitions tOSLH Pin to Pin Skew 1.3 1.5 ns (Note 13) LH Transitions tPS Duty Cycle 1.5 2.0 ns (Note 14) LH –HL Skew tOST Pin to Pin Skew 1.7 2.5 ns (Note 13) LH/HL Transitions tPV Device to Device Skew 2.0 3.0 ns (Note 15) LH/HL Transitions Symbol Parameter Typ Units Conditions TA /c32 25/c113 C CIN Input Capacitance 5 pF V CC /c32 0.0V (OEn, T/Rn) CI/O (Note 16) Output Capacitance 11 pF V CC /c32 5.0V (An, Bn)

7 www.fairchildsemi.com 74ABT16245 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

www.fairchildsemi.com 8 74ABT16245 16-Bit Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com