74ABT16244 FAIRCHILD | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

I Separate control logic for each nibble I 16-bit version of the ABT244 I Outputs sink capability of 64 mA, source capability of 32 mA I Guaranteed output skew I Guaranteed multiple output switching specifications I Output switching specified for both 50 pF and 250 pF loads I Guaranteed simultaneous switching noise level and dynamic threshold performance I Guaranteed latchup protection I High impedance glitch free bus loading during entire power up and power down cycle I Non-destructive hot insertion capability Ordering Code: Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram Order Number Package Number Package Description 74ABT16244CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74ABT16244CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OE n Output Enable Inputs (Active LOW) I0–I15 Inputs O 0–O 15 Outputs

www.fairchildsemi.com 2 74ABT16244 Truth Tables H /c32 HIGH Voltage Level L /c32 LOW Voltage Level X /c32 Immaterial Z /c32 High Impedance Functional Description The ABT16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagram Inputs Outputs OE 1 I0–I3 O0–O 3 L L L L H H H X Z Inputs Outputs OE 2 I4–I7 O4–O 7 L L L L H H H X Z Inputs Outputs OE 3 I8–I11 O8–O 11 L L L L H H H X Z Inputs Outputs OE 4 I12–I15 O12–O 15 L L L L H H H X Z

3 www.fairchildsemi.com 74ABT16244 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Note 3: Guaranteed but not tested. Storage Temperature /c16 65/c113 C to /c14 150/c113 C Ambient Temperature under Bias /c16 55/c113 C to /c14 125/c113 C Junction Temperature under Bias /c16 55/c113 C to /c14 150/c113 C VCC Pin Potential to Ground Pin /c16 0.5V to /c14 7.0V Input Voltage (Note 2) /c16 0.5V to /c14 7.0V Input Current (Note 2) /c16 30 mA to /c14 5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State /c16 0.5V to 5.5V in the HIGH State /c16 0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) DC Latchup Source Current /c16 500 mA Over Voltage Latchup (I/O) 10V Free Air Ambient Temperature /c16 40/c113 C to /c14 85/c113 C Supply Voltage /c14 4.5V to /c14 5.5V Minimum Input Edge Rate (/c39 V//c39 t) Data Input 50 mV/ns Enable Input 20 mV/ns Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage /c16 1.2 V Min I IN /c32 /c16 18 mA VOH Output HIGH Voltage 2.5 V Min I OH /c32 /c16 3 mA

2.0 V Min I OH /c32 /c16 32 mA

VOL Output LOW Voltage 0.55 V Min I OL /c32 64 mA IIH Input HIGH Current 1 /c80 A M a x VIN /c32 2.7V (Note 3) 1V IN /c32 VCC IBVI Input HIGH Current 7 /c80 A M a x V IN /c32 7.0V Breakdown Test IIL Input LOW Current /c16 1 /c80 A M a x VIN /c32 0.5V (Note 3) /c16 1V IN /c32 0.0V VID Input Leakage Test 4.75 V 0.0 I ID /c32 1.9 /c80 A All Other Pins Grounded IOZH Output Leakage Current 10 /c80 A 0 /c16 5.5V VOUT /c32 2.7V; OEn /c32 2.0V IOZL Output Leakage Current /c16 10 /c80 A 0 /c16 5.5V VOUT /c32 0.5V; OEn /c32 2.0V IOS Output Short-Circuit Current /c16 100 /c16 275 mA Max V OUT /c32 0.0V ICEX Output HIGH Leakage Current 50 /c80 A M a x V OUT /c32 VCC IZZ Bus Drainage Test 100 /c80 A 0 . 0 V OUT /c32 5.5V All Other Pins GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 60 mA Max All Outputs LOW ICCZ Power Supply Current 2.0 mA Max OE n /c32 VCC All Others at VCC or GND ICCT Additional ICC /Input Outputs Enabled 2.5 mA V I /c32 VCC /c16 2.1V Outputs 3-STATE 2.5 mA Max Enable Input V I /c32 VCC /c16 2.1V Outputs 3-STATE 50 /c80 A Data Input V I /c32 VCC /c16 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ Max Outputs Open, OEn /c32 GND (Note 3) 0.1 MHz One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 4 74ABT16244 Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of outputs defined as (n). n /c16 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Extended AC Electrical Characteristics Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: The 3-STATE delay times are dominated by the RC network (500/c58 , 250 pF) on the output and have been excluded from the datasheet. Symbol Parameter Min Typ Max Units VCC Conditions C L /c32 50 pF, RL /c32 500/c58 VOLP Quiet Output Maximum Dynamic VOL 0.4 0.7 V 5.0 T A /c32 25/c113 C (Note 4) VOLV Quiet Output Minimum Dynamic VOL /c16 1.3 /c16 1.0 V 5.0 T A /c32 25/c113 C (Note 4) VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.0 V 5.0 T A /c32 25/c113 C (Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.4 V 5.0 T A /c32 25/c113 C (Note 6) VILD Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 T A /c32 25/c113 C (Note 6) Symbol Parameter TA /c32/c14 25/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Units VCC /c32/c14 5V V CC /c32 4.5V–5.5V CL /c32 50 pF C L /c32 50 pF Min Typ Max Min Max ns ns ns Symbol Parameter /c16 40/c113 C to /c14 85/c113 C TA /c32 /c16 40/c113 C to /c14 85/c113 C T A /c32 /c16 40/c113 C to /c14 85/c113 C Units CL /c32 50 pF C L /c32 250 pF C L /c32 250 pF

16 Outputs Switching 1 Output Switching 16 Outputs Switching

(Note 7) (Note 8) (Note 9) Min Typ Max Min Max Min Max fTOGGLE Max Toggle Frequency 100 MHz ns ns tPHZ Output Disable Time 1.0 6.7 (Note 10) (Note 10) ns tPLZ 1.0 6.7

5 www.fairchildsemi.com 74ABT16244 Skew Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL ), LOW-to-HIGH (tOSLH ), or any combination switching LOW-to-HIGH and/or HIGH-to- LOW (tOST ). The specification is guaranteed but not tested. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC ) from device to device. This specification is guaranteed but not tested. Capacitance Note 16: C OUT is measured at frequency f /c32 1 MHz; per MIL STD-883, Method 3012. Symbol Parameter TA /c32 /c16 40/c113 C to /c14 85/c113 CT A /c32 /c16 40/c113 C to /c14 85/c113 C Units VCC /c32 4.5V–5.5V V CC /c32 4.5V–5.5V CL /c32 50 pF C L /c32 250 pF

16 Outputs Switching 16 Outputs Switching

(Note 11) (Note 12) Max Max tOSHL Pin to Pin Skew 1.0 1.5 ns (Note 13) HL Transitions tOSLH Pin to Pin Skew 1.0 1.5 ns (Note 13) LH Transitions tPS Duty Cycle 1.5 1.5 ns (Note 14) LH –HL Skew tOST Pin to Pin Skew 1.7 2.0 ns (Note 13) LH/HL Transitions tPV Device to Device Skew 2.0 2.5 ns (Note 15) LH/HL Transitions Symbol Parameter Typ Units Conditions TA /c32 25/c113 C CIN Input Capacitance 5.0 pF V CC /c32 5.0V COUT (Note 16) Output Capacitance 9.0 pF V CC /c32 5.0V

7 www.fairchildsemi.com 74ABT16244 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

www.fairchildsemi.com 8 74ABT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com