SN54ABT16240A_06 TI | Alldatasheet
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SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Members of the Texas Instruments Widebus Family /C0068State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation /C0068Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C /C0068Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise /C0068Flow-Through Architecture Optimizes PCB Layout /C0068High-Drive Outputs (–32-mA IOH , 64-mA IOL ) /C0068Latch-Up Performance Exceeds 500 mA Per JESD 17 /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
The ’ABT16240A devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide inverting outputs and symmetrical active-low output-enable (OE ) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16240A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16240A is characterized for operation from –40°C to 85°C. Copyright 1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 V CC 4Y1 4Y2 GND 4Y3 4Y4 4OE 2OE 1A1 1A2 GND 1A3 1A4 V CC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V CC 4A1 4A2 GND 4A3 4A4 3OE SN54ABT16240A . . . WD PACKAGE SN74ABT16240A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(each 4-bit buffer) INPUTS OUTPUT OE A Y L H L L LH H X Z logic symbol† 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 EN1 EN4 1OE 2OE 3OE 4OE EN2 EN3 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3) SN54ABT16240A SN74ABT16240A UNIT MIN MAX MIN MAX UNIT VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA Δt/Δv Input transition rise or fall rate Outputs enabled 10 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C SN54ABT16240A SN74ABT16240A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN MAX MIN MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VOH VCC = 5 V, IOH = –3 mA 3 3 3 VVOH VCC =45V IOH = –24 mA 2 2 V VCC = 4.5 V IOH = –32 mA 2* 2 VOL VCC =45V IOL = 48 mA 0.55 0.55 VVOL VCC = 4.5 V IOL = 64 mA 0.55* 0.55 V Vhys 100 mV II VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA IOZH VCC = 5.5 V, VO = 2.7 V 10 10 10 µA IOZL VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA IO ‡ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA VCC = 5.5 V, Outputs high 3 3 3 ICC VCC = 5.5 V, IO = 0, Outputs low 34 34 34 mA VI = VCC or GND Outputs disabled 3 3 3 Data VCC = 5.5 V, One input at 3.4 V, Outputs enabled 1 1.5 1 ΔICC § inputs Other inputs at VCC or GND Outputs disabled 0.05 1 0.05 mA Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 1.5 1.5 C i VI = 2.5 V or 0.5 V 3.5 pF C o VO = 2.5 V or 0.5 V 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16240A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH A Y ns tPHL A Y ns tPZH OE Y ns tPZL OE Y ns tPHZ OE Y ns tPLZ OE Y 1.4 3 5.1 1.4 5.7 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT16240A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH A Y 1 2.7 3.8 1 4.7 ns tPHL A Y ns tPZH OE Y ns tPZL OE Y ns tPHZ OE Y ns tPLZ OE Y 1.4 3 5.1 1.4 5.6 ns
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9319901MXA ACTIVE CFP WD 48 1 TBD A42 SNPB N / A for Pkg Type 74ABT16240ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ABT16240ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ABT16240ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADGGRG ACTIVE TSSOP DGG 48 TBD Call TI Call TI SN74ABT16240ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16240ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ABT16240AWD ACTIVE CFP WD 48 1 TBD A42 SNPB N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2006 Addendum-Page 1
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 4040176/D 10/97
48 LEADS SHOWN
0.610 (18,80) 0.710 (18,03) 0.7400.640 0.390 (9,91) 0.370 (9,40) 0.870 (22,10) 1.130 (28,70) A 0.120 (3,05) 0.075 (1,91) LEADS** NO. OF A MIN A MAX (16,26) (15,49) 0.025 (0,635) 0.009 (0,23) 0.004 (0,10) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 0.014 (0,36) 0.008 (0,20) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA GDFP1-F56 and JEDEC MO-146AB
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040048/E 12/01
48 PINS SHOWN
0.730 (18,54) 0.720 (18,29) 4828 0.370 (9,40) (9,65) 0.380 Gage Plane DIM 0.420 (10,67) 0.395 (10,03) A MIN A MAX 0.010 (0,25) PINS ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) Seating Plane 0.020 (0,51) 0.040 (1,02) 0.008 (0,203) 0.0135 (0,343) 0.008 (0,20) MIN A 0.110 (2,79) MAX 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) M0.005 (0,13) 0.025 (0,635) 0°–/C02578° 0.005 (0,13) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97 0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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