74LS92 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 3
Technical content
54LS/74LS92 mao ~ [razr DIVIDE-BY-TWELVE COUNTER ne [2] [is}Ne ne [3] Lia}o0 neLa] [alo, vec [5] [79] eno wef] [Jo. wn [7] [a0 DESCRIPTION —The ‘92 is a 4-stago ripple counter containing a high LOGICISY SOF speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the clocks and force all outputs to the LOW state. 14—o| cro ORDERING CODE: See Section 9 1—o| cP: COMMERCIAL GRADE| MILITARY GRADE MR_So A: 2 Oe PIN pKa PKGS out Voc = +5.0 V +5%, Vec = +6.0 V +10%, TYPE (. 2) Ta=0°C to+70°C | Ta=-85°C to +126°C aT o7 wie 8 BE [afewemere [tm] gens GND = Pin 10 Beramic | a | 7492ADG, 74/9206 _|5492ADM, 54LS92DM Dal SS Dt) Mer T492hFC, 7ALS92FC | S492AFM, 54LS92FM INPUT LOADING/FAN-OUT: See Section 3 for ULL. definitions 84/74 (UL) 54/7ALS (U.L.) PIN NAMES DESCRIPTION Reon etiowl CPo +2 Section Clock Input 2.0/2.0 0,125/1.5 _ ‘Active Falling Edge) CP +6 Section Clock Input 3.0/3.0 0.250/2.0 (Active Falling Edge) MRi, MR2 Asynchronous Master Reset Input 1.0/1.0 0,5/0.25, (Active HIGH) Q +2 Section Output 20/10 10/5.0 (2.5) Qi—O3 +6 Section Outputs 20/10 10/5.0 (2.5) The Gp output ls guaranteed to drive the full rated fan-out plus the GFF Input
FUNCTIONAL DESCRIPTION — The ‘92 is a 4-bit ripple type divide-by-twelve counter. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divideby-six section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to- LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes, The Qo output of each device is designed and specified to drive the rated fan-out plus the CPt input of the device. A gated AND asynchronous Master Reset (MR1, MP2) is provided which overrides the clocks and resets (clears) all the flip-flops. Since the output from the divide-by-two section is not internally connected tothe succeeding stages, the devices may be operated in various counting modes: A. Modulo 12, Divide-By-Twelve Counter — The GP; input must be externally connected to the Qo output. The GPo input receives the incoming count and Qa produces a symmetrical divide-by-twelve square wave output. : B. Divide-By-Two and Divide-By-Six Counter —No external interconnections are required. The first flip- flop is used as a binary element for the divide-by-two function. The CPi input Is used to obtain divide-by-three operation at the Qi and Qe outputs and divide-by-six operation at the Qs output. MODE SELECTION TABLE TRUTH TABLE Ines ouTPUTS count |__OUTPUT Qo 1 G2 Qs HoHfte CLL tJeoeoue Lou Count 2]feuneucte HOoL Count 3 ]H HLL LoL Count Alana n H = HIGH Voltage Level 5 HOL HOL UZ Low Vottage Levo! 6 jt ucuun 7 |H LU H e jt HUH 9 |H HL OH wo Ju tL HH a fH ob HOH NOTE: Output Qo connected to CF LoGic DIAGRAM cm —der afer Lee LH der er, co ny wn—4_)° Qo a Qa Qs
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) i Input HIGH Current, CPo [to] 02] ma__| Voc =Max, Vin=55V ti Input HIGH Current, GP1 [10] oa] mA | Voc=Max, Vin=55V AC CHARACTERISTICS: Voc = 5.0 V, Ta = 25°C (See Section 3 for waveforms and load configurations) SYMBOL PARAMETER C= 15 pF(C.=15 pF| UNITS CONDITIONS RL = 4002 4 Maximum Count Frequency, ; frnax Ser input Figs. 3-1, 3-9 Maximum Count Frequency, {max ep 16 16 MHz | Figs. 3-1, 3-9 Pun Propagation Delay 16 16 te Po to Qo 18 18 aa tPLH Propagation Delay 48 48 tent Po to Qs 50 50 eau ten Propagation Delay 16 teHt GP; to Qi 21 Figs. 3-1, 3-6 tPLH Propagation Delay 16 1. 34 tL GP; to Qe a Figs. 3-1, 3-8 ten Propagation Delay 32 32 ’ tent GPi to Oa 35 35 Figs. 3-1, 3-9 cm Propagation Delay, MAtoG, | 40 | 40 | —ns_‘|_ Figs. 3-1, 3-17 AC OPERATING REQUIREMENTS: Vcc = 5.0 V, Ta = 25°C SYMBOL PARAMETER Sa74L$_| units CONDITIONS Pin in