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IDT74SSTU32864 RENESAS | Alldatasheet

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COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O APRIL 2006 2006 Integrated Device Technology, Inc. DSC-5980/27c IDT74SSTU32864/ A/C/D/G COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O DESCRIPTION: The SSTU32864 is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V V DD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from the A configuration (when low) to B configuration (when high). The C1 input controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when high). This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V REF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS and CSR inputs and will gate the outputs from changing states when both D CS and CSR inputs are high. If either DCS or CSR input is low, the device will function normally. The RESET input has priority over the DCS control and will force the inputs low. If the DCS control functionality is not desired, then the CSR input can be hard- wired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs. The SSTU32864G has two slew control pins (Z OH and Z OL) used to optimize the signal integrity on the DIMM. APPLICATIONS:

• Ideally suited for DDR2-400/533 (PC2 - 3200/ 4200) registered DIMM applications
• Along with CSPU877/A/D, zero delay PLL clock buffer, provides complete solution for DDR2-400/533 DIMMs
• SSTU32864 is optimized for DDR2 Raw cards B and C
• SSTU32864A is optimized for DDR2 Raw card A
• SSTU32864C/D/G are optimized for DDR2 Raw cards A, B, and C
• SSTU32864G has control pins for output slew rate control FEATURES:
• 1:1 and 1:2 registered buffer
• 1.8V Operation
• SSTL_18 style clock and data inputs
• Differential CLK input
• Control inputs compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
• Maximum operating frequency: 340MHz
• Available in 96-pin LFBGA package The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTIONAL BLOCK DIAGRAM (1:2) O

1 QxA

R R R QCSA QCSB QODTA QODTB QCKEA QCKEB

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O PIN CONFIGURATION (TYPE A) 96-PIN LFBGA 1:2 REGISTER (TYPE A, FRONTSIDE) TOP VIEW PIN CONFIGURATION (TYPE B) 96-PIN LFBGA 1:2 REGISTER (TYPE B, BACKSIDE) TOP VIEW AB C DE F G HJ K LMNPRT Q2B Q3B Q5B Q6B Q8B Q9B ZOH QCSB QCSA QODTBQCKEB Q13B Q14B VDD VREF D2 D3 D5 D6 CLK RESET D8 D9 D10 D11 Q2A Q3A Q5A Q6A Q8A Q9A ZOL QODTAQCKEA Q13A Q14A NC CLK VDD VREF DCKE NC NC NC NC NC NC NC NC NC NC NC NC DODT GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD DCS CSR Q10B Q11B Q10A Q11A Q12B Q12A NC D12 D14D13 AB C DEF G H J K LM NPRT Q13BQ10BQ9BQ8BQCSB QCSA Q6BQ5B ZOH ZOL QODTB QCKEBQ4BQ3BQ2BQ1B D13D12D9D8D6D5 CLK RESET D4D3D2D1 Q13AQ10AQ9AQ8AQ6AQ5A QODTA QCKEAQ4AQ3AQ2AQ1A NC CLK DCKE NCNCNCNCNCNCNCNCNCNCNC DODT NC VDD VREF VDD VREF GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD DCS CSR Q12B Q12A NC D10

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTIONAL BLOCK DIAGRAM (1:1) O Qx R RESET CLK1 CLK1 VREF Dx DCKE DODT DCS TO 21 OTHER CHANNELS CSR QOTD R QCS R QCKE R

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O PIN CONFIGURATION 96-PIN LFBGA 1:1 REGISTER TOP VIEW AB C DEF G HJ K LMNPRT Q15 Q16 Q17 Q18 ZOLNC QCS NC Q19 Q20 Q21 Q22 D2 D3 D5 D6 CLK RESET D8 D9 D10 D11 Q2 Q3 Q5 Q6 Z OHQODTQCKE Q8 Q9 Q10 Q11 NC DCS CLK DCKE NC DODT NC D15 D16 D17 D18 D19 D20 D21 D22 VDD VREF VDD VREF GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD GND GND VDD VDD CSR Q23 Q24 Q25 Q12 Q13 Q14 D23 D24 D25 NC D12 D13 D14 *Rows 3 and 4 are reserved for V DD and GND.

96 BALL LFBGA PACKAGE ATTRIBUTES

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs Qx Q CSx QODTx, QCKEx RESET DCS CSR CLK CLK Dx, DODT, DCKE Outputs Output Outputs HLL ↑↓ LL L L HLL ↑↓ HH L H H L L L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HLH ↑↓ LL L L HLH ↑↓ HH L H H L H L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HH L ↑↓ LL H L HH L ↑↓ HH H H H H L L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HHH ↑↓ LQ 0 (2) HL HHH ↑↓ HQ 0 (2) HH H H H L or H L or H X Q 0 (2) Q0 (2) Q0 (2) L X or Floating X or Floating X or Floating X or Floating X or Floating L L L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. Output level before the indicated steady-state conditions were established. MODE SELECT C0 C1 Device Mode 0 0 1:1 25-bit to 25-bit 0 1 1:2 14-bit to 28-bit, Front (Type A) 1 0 Reserved 1 1 1:2 14-bit to 28-bit, Back (Type B) OUTPUT CONTROL (SSTU32864G) ZOH ZOL Output Slew Rate 0 0 Standard 0 1 Highest 1 0 Low 1 1 High

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O TERMINAL FUNCTIONS (ALL PINS) Terminal Electrical Name Characteristics Description GND Ground Input Ground VDD 1.8V nominal Power Supply Voltage VREF 0.9V nominal Input Reference Voltage ZOH(1) LVCMOS Output Slew Rate Control ZOL(1) LVCMOS Output Slew Rate Control CLK Differential Input Positive Master Clock Input CLK Differential Input Negative Master Clock Input C x LVCMOS Input Configuration Control Inputs RESET LVCMOS Input Asynchronous Reset Input. Resets registers and disables V REF data and clock differential-input receivers. CSR, DCS SSTL_18 Input Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH. Dx SSTL_18 Input Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. DODT SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls DCKE SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls Q x 1.8V CMOS Data Outputs that are suspended by the D CS and CSR controls QCSx 1.8V CMOS Data Output that will not be suspended by the D CS and CSR controls QODTx 1.8V CMOS Data Output that will not be suspended by the D CS and CSR controls QCKEx 1.8V CMOS Data Output that will not be suspended by the D CS and CSR controls ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max. Unit VDD Supply Voltage Range –0.5 to 2.5 V VI(2,3) Input Voltage Range –0.5 to 2.5 V VO(2,3) Output Voltage Range –0.5 to VDD +0.5 V IIK Input Clamp Current V I < 0 ±50 mA VI > VDD IOK Output Clamp Current V O < 0 ±50 mA VO > VDD IO Continuous Output Current, ±50 mA VO = 0 to VDD VDD Continuous Current through each ±100 mA VDD or GND TSTG Storage Temperature Range –65 to +150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. NOTE: 1. The signals will be left unconnected for the SSTU32864/A/C/D.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O OPERATING CHARACTERISTICS, TA = 25ºC (1,2) Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 1.7 — 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V VTT Termination Voltage V REF– 40mV V REF VREF+ 40mV V VI Input Voltage 0 — V DD V VIH AC High-Level Input Voltage Data Inputs V REF+ 250mV — — V VIL AC Low-Level Input Voltage Data Inputs — — V REF– 250mV V VIH DC High-Level Input Voltage Data Inputs V REF+ 125mV — — V VIL DC Low-Level Input Voltage Data Inputs — — V REF– 125mV V VIH High-Level Input Voltage RESET, Cx 0.65 * VDD —— V VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V VID Differential Input Voltage CLK, CLK 600 — — mV IOH High-Level Output Current — — –8 mA IOL Low-Level Output Current — — 8 TA Operating Free-Air Temperature 0 — 70 °C NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW. Symbol Parameter Test Conditions Min. Typ. Max. Unit VOH VDD = 1.7V to 1.9V, IOH = –6mA 1.2 — — V VOL VDD = 1.7V to 1.9V, IOL = 6mA — — 0.5 V II All Inputs V I = VDD or GND –5 — 5 μA IDD Static Standby I O = 0, V DD = 1.9V, RESET = GND — — 100 μA Static Operating I O = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) —— 4 0 m A IDDD Dynamic Operating I O = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),— — — μA/Clock (Clock Only) CLK and CLK Switching 50% Duty Cycle. MHz IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode — — — Dynamic Operating V I = VIH (AC) or VIL (AC), CLK and CLK Switching at μA/Clock (Per Each Data Input) 50% Duty Cycle. One Data Input Switching at 1:2 Mode — — — MHz/Data Half Clock Frequency, 50% Duty Cycle. Input Data Inputs V I = VREF ± 250mV 2.5 — 3.5 CI CLK and CLK VICR = 0.9V, VID = 600mV 2 — 3 pF RESET VI = VDD or GND 2 — 4 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ±0.1V

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V ± 0.1V Symbol Parameter Min. Max. Unit fCLOCK(1) Clock Frequency — 340 MHz tw Pulse Duration, CLK, CLK HIGH or LOW 1 — ns tACT(2) Differential Inputs Active Time — 10 ns tINACT(3) Differential Inputs Inactive Time — 15 ns DCS before CLK↑, CLK↓, CSR HIGH 0.7 — tSU Setup Time D CS before CLK↑, CLK↓, CSR LOW 0.5 — ns DODT, CSR, Data, and DCKE before CLK↑, CLK↓ 0.5 — tH Hold Time Data, DCS, CSR, DCKE, and DODT after CLK↑, CLK↓ 0.5 — ns NOTES: 1. 270MHz max clock frequency for parts assembled and tested prior to WW37. 2. Data and V REF inputs must be low a minimum time of t ACT max, after RESET is taken HIGH. 3. Data, V REF, and clock inputs must be held at valid levels (not floating) a minimum time of t INACT max, after RESET is taken LOW. SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V ± 0.1V Symbol Parameter Min Max. Unit fMAX 340 — M H z tPDM(2) CLK and CLK to Q 1.41 2.15 ns tPDMSS(2,3) CLK and CLK to Q (simultaneous switching) — 2.35 ns tRPHL RESET to Q — 3 ns dV/dt_r Output slew rate from 20% to 80% 1 4 V/ns dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns dV/dt_Δ(4) Output slew rate from 20% to 80% — 1 V/ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O CL = 30 pF RL = 1KΩ DUT Out RL = 100Ω CLK Inputs TL = 50Ω TL = 350ps, 50Ω Test Point VDD VDD/2 LVCMOS RESET Input IDD VDD/2 tINACT tACT 10% 90% CLK VICR VID tPLH tPHL Output VOH VOL VICR VTT VTT VOH VOL VIH VIL tRPHL VDD/2 VTT LVCMOS RESET Input Output VICR VIDVICRInput tW VREF VIH VIL VREFInput VICR VID tSU tH CLK CLK VDD RL = 1KΩ Test Point Test Point CLK CLK CLK TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) Voltage Waveforms - Pulse Duration NOTES: 1. C L includes probe and jig capacitance. 2. I DD tested with clock and data inputs held at V DD or GND, and I O = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z O = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. V TT = V REF = V DD/2 6. V IH = V REF + 250mV (AC voltage levels) for differential inputs. V IH = V DD for LVCMOS input. 7. V IL = V REF - 250mV (AC voltage levels) for differential inputs. V IL = GND for LVCMOS input. 8. V ID = 600mV. 9. t PLH and t PHL are the same as t PDM. Load Circuit Voltage Waveforms - Setup and Hold Times Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Propagation Delay Times Voltage and Current Waveforms Inputs Active and Inactive Times

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O CL = 10 pF RL = 50ΩDUT Out Test Point VDD VOH 80% 20% VOL Output dv_f dt_f CL = 10 pF RL = 50Ω DUT Out Test Point VOL 20% 80% VOH Output dv_r dt_r TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) NOTES: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z O = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). Load Circuit: High-to-Low Slew-Rate Adjustment Voltage Waveforms: High-to-Low Slew-Rate Adjustment Load Circuit: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Low-to-High Slew-Rate Adjustment

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32864/A/C/D/G 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

ORDERING INFORMATION

PackageDevice TypeTemp. Range BF BFG Low Profile, Fine Pitch, Ball Grid Array LFBGA - Green 1:1 and 1:2 Registered Buffer with 1.8V SSTL I/O 0°C to +70°C SSTU32 864 864A 864C 864D 864G X Shipping Carrier Blank Tape and reel Tray

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