74823CTQG

IDT74FCT823AT RENESAS | Alldatasheet

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INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER February 19, 2009INDUSTRIAL TEMPERATURE RANGE The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2006 Integrated Device Technology, Inc. DSC-5487/4 FEATURES:

• A and C grades  Low input and output leakage ≤≤≤≤≤1µA (max.)  CMOS power levels  True TTL input and output compatibility: OH = 3.3V (typ.) –V OL = 0.3V (typ.)  High Drive outputs (-15mA I OH, 48mA IOL)  Meets or exceeds JEDEC standard 18 specifications  Power off disable outputs permit "live insertion"  Available in the SOIC and QSOP packages FUNCTIONAL BLOCK DIAGRAM IDT74FCT823AT/CTHIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER DESCRIPTION: The FCT823T series is built using an advanced dual metal CMOS technology. The FCT823T series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT823T is a 9-bit wide buffered register with Clock Enable (EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823T high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low- capacitance bus loading in high-impedance state. D CP Q QCLD CP Q QCL D0 DN Y0 YN EN CLR CP OE

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER PIN CONFIGURATION Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to V CC+0.5 V TSTG Storage Temperature –65 to +150 ° C IOUT DC Output Current –60 to +120 mA ABSOLUTE MAXIMUM RATINGS(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance V IN = 0V 6 10 pF COUT Output Capacitance V OUT = 0V 8 12 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. FUNCTION TABLE(1) Internal/ Inputs Outputs OE CLR EN Dx CP Qx Yx Function HHLL ↑ L Z High Z HHLH ↑ HZ H L X X X L Z Clear LL X X X L L H H H X X N C Z Hold LH HX X N C N C HHLL ↑ L Z Load HHLH ↑ HZ LHLL ↑ LL LHLH ↑ HH NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level NC = No Change ↑ = LOW-to-HIGH Transition Z = High Impedance 169 VCC CP OE 1411 GND CLR EN SOIC/ QSOP TOP VIEW Pin Names I/O Description Dx I D Flip-Flop Data Inputs CLR I When the clear input is LOW and OE is LOW, the Qx outputs are LOW. When the clear input is HIGH, data can be entered into the register. CP I Clock Pulse for the Register; enters data into the register on the LOW-to-HIGH transition. Y x O Register 3-State Outputs EN I Clock Enable. When the clock enable is LOW, data on the Dx output is transferred to the Qx output on the LOW-to-HIGH transition. When the clock enable is HIGH, the Qx outputs do not change state, regardless of the data or clock input transitions. OE I Output Control. When the OE is HIGH, the Yx outputs are in the high-impedance state. When the OE is LOW, the TRUE register data is present at the Yx outputs. PIN DESCRIPTION

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current(4) VCC = Max. V I = 2.7V — — ±1µ A IIL Input LOW Current(4) VCC = Max. V I = 0.5V — — ±1µ A IOZH High Impedance Output Current(4) VCC = Max., V I = VCC (Max.) V I = 2.7V — — ±1µ A IOZL VI = 0.5V — — ±1 II Input HIGH Current(4) VCC = Max., V I = VCC (Max.) — — ±1µ A VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V VH Input Hysteresis — — 200 — mV ICC Quiescent Power Supply Current V CC = Max. — 0.01 1 mA VIN = GND or VCC DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: T A = –40°C to +85°C, VCC = 5.0V ±5% NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5µA at T A = –55°C. 5. This parameter is guaranteed but not tested. Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VOH Output HIGH Voltage V CC = Min I OH = –8mA 2.4 3.3 — V VIN = VIH or VIL IOH = –15mA 2 3 — VOL Output LOW Voltage V CC = Min I OL = 48mA — 0.3 0.5 V VIN = VIH or VIL IOS Short Circuit Current V CC = Max., V O = GND(3) –60 –120 –225 mA IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤≤≤≤≤ 4.5V — — ±1µ A OUTPUT DRIVE CHARACTERISTICS

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ΔICC Quiescent Power Supply Current V CC = Max. — 0.5 2 mA TTL Inputs HIGH V IN = 3.4V(3) ICCD Dynamic Power Supply V CC = Max. V IN = VCC — 0.15 0.25 mA/ Current(4) Outputs Open V IN = GND MHz OE = EN = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. V IN = VCC — 1.5 3.5 mA Outputs Open V IN = GND fCP = 10MHz 50% Duty Cycle OE = EN = GND V IN = 3.4V — 2 5.5 One Bit Toggling V IN = GND at fi = 5MHz V CC = Max. V IN = VCC — 3.8 7.3 (5) Outputs Open V IN = GND fCP = 10MHz 50% Duty Cycle OE = EN = GND V Eight Bits Toggling V IN = GND at fi = 2.5MHz NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Per TTL driven input; (V IN = 3.4V). All other inputs at V CC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. I C = IQUIESCENT + IINPUTS + IDYNAMIC IC = I CC + ΔICC DHNT + I CCD (f CP/2+ fiNi) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (V IN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D H ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at f i All currents are in milliamps and all frequencies are in megahertz. POWER SUPPLY CHARACTERISTICS

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT823AT FCT823CT Symbol Parameter Condition (1) Min.(2) Max. Min .(2) Max. Unit tPLH Propagation Delay C L = 50pF 1.5 10 1.5 6 ns tPHL CP to Yx (OE = LOW) R L = 500Ω CL = 300pF(4) 1.5 20 1.5 12.5 ns RL = 500Ω tSU Set-up Time HIGH or LOW Dx to CP C L = 50pF 4 — 3 — ns tH Hold Time HIGH or LOW Dx to CP R L = 500Ω 2 — 1.5 — ns tSU Set-up Time HIGH or LOW EN to CP 4 — 3 — ns tH Hold Time HIGH or LOW EN to CP 2 — 0 — ns tPHL Propagation Delay, CLR to Yx 1.5 14 1.5 8 ns tREM Recovery Time CLR to CP 6 — 6 — ns tW Clock Pulse Width HIGH or LOW 7 — 6 — ns tW CLR Pulse Width LOW 6 — 6 — ns tPZH Output Enable Time OE to Yx C L = 50pF 1.5 12 1.5 7 ns tPZL RL = 500Ω CL = 300pF(4) 1.5 23 1.5 12.5 ns RL = 500Ω tPHZ Output Disable Time OE to Yx C L = 5pF(4) 1.5 7 1.5 6 ns tPLZ RL = 500Ω CL = 50pF 1.5 8 1.5 6.5 ns RL = 500Ω NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. This condition is guaranteed but not tested.

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER Pulse Generator R T D.U.T VCC VIN C L VOUT 50pF 500W 500W 7.0V 1.5V 1.5V 1.5V 1.5V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 1.5V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 1.5V tPLH tPHL tPHL VOL CONTROL INPUT 1.5V 3.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZtPZL tPZH tPHZ 3.5V 1.5V 1.5V ENABLE DISABLE VOH PRESET CLEAR CLOCK ENABLE ETC. Octal Link Octal Link Octal Link Octal Link Octal Link TEST CIRCUITS AND WAVEFORMS Propagation Delay Test Circuits for All Outputs Enable and Disable Times Set-Up, Hold, and Release Times Pulse Width NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open SWITCH POSITION DEFINITIONS: C L = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator.

INDUSTRIAL TEMPERATURE RANGE IDT74FCT823AT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER

ORDERING INFORMATION

Temp. Range XXXX Device Type X Package SO SOG Q QG 823AT 823CT Small Outline IC SOIC - Green Quarter-size Small Outline Package QSOP - Green Bus Interface Register 74 - °C to +85°C FCT

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