7481

7480 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 7480/7481 group is the single-chip microcomputer adopting the silicon gate CMOS process. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed in the same memory space. Having built-in serial I/O, A-D converter, and watchdog timer, this single-chip microcomputer is useful for control of automobiles, of- fice automation equipment and home electric appliances. The 7480/7481 group includes multiple types which differ in the memory type, size, and package.

FEATURES

(at 8 MHz clock input oscillation frequency) (P0, P1, P4, P5) 24 (7481 group) (P2, P3) 12 (7481 group) l Built-in programmable pull-up transistors (P0, P1) (P4, P5) 8 (7481 group) 8-bit x 8 channels (7481 group) l Built-in watchdog timer (at [2.2 V CC -2] MHz clock input oscillation frequency) 4.5 to 5.5 V (at 8 MHz clock input oscillation frequency) (at 8 MHz clock input oscillation frequency and 5 V power source voltage)

APPLICATIONS

Automobiles, office automation equipment, home electric appli- ances, etc. Fig. 1 Pin configuration (top view) PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. 16 17 M37480MX-XXXSP M37480MXT-XXXSP M37480E8-XXXSP M37480E8T-XXXSP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET V CC Outline 32P4B 16 17 M37480MX-XXXFP M37480MXT-XXXFP M37480E8-XXXFP M37480E8T-XXXFP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN X OUT V SS P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET VCC Outline 32P2W-A PIN CONFIGURATION

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 2 Pin configuration (top view) P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P20/IN0 V REF X IN X OUT V SS AV SS P30/INT0 V CC P51 P50 RESET P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 2 P33 P32 P31/INT1 P43 P42 P17/SRDY P07 P06 P05 P04 P52 P16/SCLK P15/TXD P14/RXD P53 VSS M37481MX-XXXFP M37481MXT-XXXFP M37481E8-XXXFP M37481E8T-XXXFP Outline 44P6N-A M37481MX-XXXSP M37481MXT-XXXSP M37481E8-XXXSP M37481E8T-XXXSP M37481E8SS P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET VCC 17 26 P53 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P52 P51 P50 P43 P42 Outline 42P4B 42S1B-A

Notice: This is not a final specification. Some parametric limits are subject to change. Table 1. 7480/7481 group product list

18 I/O ports

24 I/O ports

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 3 ROM/RAM development schedule Note: Regarding the models being developed and planned, the development schedule may be reviewed. In case of the models be- ing planned, the development of them may be stopped. 7480/7481 GROUP ROM/RAM DEVELOPMENT SCHEDULE ROM size (bytes) 16K 12K 128 256 384 4480 M37480M2T-XXXSP/FP M37481M2T-XXXSP/FP M37480M4-XXXSP/FP M37480M4T-XXXSP/FP M37481M4-XXXSP/FP M37481M4T-XXXSP/FP M37480M8/E8-XXXSP/FP M37481M8/E8-XXXSP/FP M37481E8SS M37480M8T/E8T-XXXSP/FP M37481M8T/E8T-XXXSP/FP : Being developed : Being planned RAM size (bytes)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 4 Function block diagram (1) 24 23 22 19 13 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 14 15 18 17 16 A-D converter P0 (8) Serial I/O (8) Clock generating circuit RAM 448 bytes Program counter PC H (8) Program counter PC L (8) ROM 16384 bytes Accumulator A (8) Index register X (8) Index register Y (8) Stack pointer S (8) Processor status register PS (8) Timer 1 (8) Timer 2 (8) Timer X (16) Timer Y (16) Instruction decoder Control signal VCC VSS Reset input Clock output XOUT Clock input XIN (Note 2) Data bus (Note 1) 8-bit arithmetic and logical unit P3 (4) CNTR 1CNTR 0 INT1 INT0 4 M37480M8/E8-XXXSP/FP, M37480M8T/E8T-XXXSP/FP FUNCTION BLOCK DIAGRAM I/O port P4 Input port P3 VREF Reference voltage input Input port P2 I/O port P1 I/O port P0 Notes 1: 8192 bytes for M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 4096 bytes for M37480M2T-XXXSP/FP 2: 256 bytes for M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 128 bytes for M37480M2T-XXXSP/FP RESET Instruction register (8) INT1 INT0 20 21 FUNCTIONAL BLOCK DIAGRAM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 5 Function block diagram (2) 1 42 24 23 33 32 31 30 29 26 18 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 19 20 25 22 21 A-D converter P0 (8) Serial I/O (8) Clock generating circuit RAM 448 bytes Program counter PC H (8) Program counter PC L (8) ROM 16384 bytes Accumulator A (8) Index register X (8) Index register Y (8) Stack pointer S (8) Processor status register PS (8) Timer 1 (8) Timer 2 (8) Timer X (16) Timer Y (16) Instruction decoder Control signal VCC VSS Reset input Clock output XOUT Clock input XIN (Note 2) Data bus (Note 1) 8-bit arithmetic and logical unit P3 (4) CNTR 1CNTR 0 INT1 INT0 8 M37481M8/E8-XXXSP, M37481M8T/E8T-XXXSP, M37481E8SS FUNCTION BLOCK DIAGRAM I/O port I/O port P4 Input port P3 VREF Reference voltage input Input port P2 I/O port P1 I/O port P0 Notes 1: 8192 bytes for M37481M4-XXXSP, M37481M4T-XXXSP and 4096 bytes for M37481M2T-XXXSP 2: 256 bytes for M37481M4-XXXSP, M37481M4T-XXXSP and 128 bytes for M37481M2T-XXXSP RESET Instruction register (8) INT1 INT0 27 28

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 6 Function block diagram (3) 40 38 20 19 29 28 27 26 25 24 22 13 5 6 7 8 9 10 11 12 41 42 43 44 1 2 3 4 37 36 35 34 33 32 31 30 14 15 21 18 17 A-D converter P0 (8) Serial I/O (8) Clock generating circuit RAM 448 bytes Program counter PC H (8) Program counter PC L (8) ROM 16384 bytes Accumulator A (8) Index register X (8) Index register Y (8) Stack pointer S (8) Processor status register PS (8) Timer 1 (8) Timer 2 (8) Timer X (16) Timer Y (16) Instruction decoder Control signal VCC VSS Reset input Clock output XOUT Clock input XIN (Note 2) Data bus (Note 1) 8-bit arithmetic and logical unit P3 (4) CNTR 1CNTR 0 INT1 INT0 8 M37481M8/E8-XXXFP, M37481M8T/E8T-XXXFP FUNCTION BLOCK DIAGRAM I/O port P5 I/O port P4 Input port P3 VREF Reference voltage input Input port P2 I/O port P1 I/O port P0 Notes 1: 8192 bytes for M37481M4-XXXFP, M37481M4T-XXXFP and 4096 bytes for M37481M2T-XXXFP 2: 256 bytes for M37481M4-XXXFP, M37481M4T-XXXFP and 128 bytes for M37481M2T-XXXFP RESET Instruction register (8) AV SS INT1 INT0

Notice: This is not a final specification. Some parametric limits are subject to change. Table 2. Functions of 7480/7481 group

Notice: This is not a final specification. Some parametric limits are subject to change. Table 3. Pin description Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS . resistor is connected between XIN and XOUT . 8-bit I/O port. The output structure is CMOS output. units of 1 bit, and a key-on wake-up function is provided. 8-bit I/O port. The output structure is CMOS output. 2 and P13 are in common with timer output pins T0 and T1. be configured to serve as timer I/O pins CNTR0 and CNTR1. is N-channel open drain output, having built-in clamp diodes.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CPU Mode Register The stack page selection bit is assigned to the CPU mode regis- ter. This register is allocated at address 00FB16. Fig. 7 Structure of CPU mode register FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7480/7481 group uses the standard 740 family CPU. Refer to the table of 740 family addressing modes and machine instruc- tions or the MELPS 740 programming manual for details on the instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions are not available. 2. The MUL and DIV instructions are available. 3. The WIT instruction is available. (Note) 4. The STP instruction is available. (Note) Note:When using these instructions, refer to the corresponding chapter “STP and WIT instruction control” below. CPU mode register (CPUM: address 00FB16) b7 b0 Stack page selection bit (Note) 0 : Page 0 1 : Page 1 System clock division proportion selection bit 0 : f = f(XIN)/2 (high-speed mode) 1 : f = f(XIN)/8 (medium-speed mode) Not used. These bits must always be set to “0”. Watchdog timer L count source selection bit 0 : f(X IN)/8 1 : f(X IN)/16 Note : In the models of RAM size under 192 bytes, set this bit to “0”. Not used (undefined at read) Not used (undefined at read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Memory

• SFR Area This SFR area is provided in the zero page and contains the reg- isters for controlling I/O ports and timers.
• RAM RAM is used for data storage and for calling subroutines, as well as for a stack area for interrupts.
• ROM ROM is used for storing user programs and interrupt vectors. Fig. 8 Memory map
• Interrupt Vector Area The interrupt vector area is used for storing vector addresses when an interrupt is generated or at reset.
• Zero Page This area can be accessed with 2 words when the zero page ad- dressing mode is used.
• Special Page This area can be accessed with 2 words when the special page addressing mode is used.SFR area Not used Interrupt vector area 000016 007F16 008016 00BF 16 00C0 16 00FF 16 010016 013F16 01FF 16 C000 16 E000 16 F00016 FF00 16 FFE4 16 FFFF 16 Zero page Special page RAM (192 bytes) for M37480M4, M37480M8/E8, M37481M4, M37481M8/E8 RAM (128 bytes) for M37480M2, M37481M2 RAM (256 bytes) for M37480M8/E8, M37481M8/E8 RAM (64 bytes) for M37480M4, M37481M4 ROM (16384 bytes) for M37480M8/E8, M37481M8/E8 ROM (8192 bytes) for M37480M4, M37481M4 ROM (4096 bytes) for M37480M2, M37481M2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 9 SFR (Special Function Register) memory map Note: This port is not allocated in the 7480 group. 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C9 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) (Note) Edge polarity selection register (EG) A-D control register (ADCON) A-D conversion register (AD) STP instruction operation control register (STPCON) Port P5 direction register (P5D) (Note) Port P0 pull-up control register (P0PCON) Port P1 pull-up control register (P1PCON) Port P4P5 input control register (P4P5CON) Transmit/receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Bus collision detection control register (BUSARBCON) Watchdog timer H (WDTH) Timer X low-order (TXL) Timer X high-order (TXH) Timer Y low-order (TYL) Timer Y high-order (TYH) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TXM) Timer Y mode register (TYM) Timer XY control register (TXYCON) Timer 1 mode register (T1M) Timer 2 mode register (T2M) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. [Pull-up Control Registers] Ports P0 and P1 are provided with a programmable pull-up tran- sistor. When “1” is written to the pull-up control register and the direction register is in the input mode, the pull-up transistor turns on, and the port is pulled up. n Notes on Use for STP Instruction When the 7480/7481 group is executing an STP instruction, apply 0 V or the same voltage as Vcc to the following pins. If an intermediate voltage is applied to these pins, a through-cur- rent flows to the input gates and the power current increases. P4, P5, P3, P1 6, P14 [Port P4P5 Input Control Register] When ports P4 2, P43 and P5 of the 7481 group are selected for in- put, clear the corresponding direction register to “0” and set “1” to the corresponding bit of the port P4P5 input control register. Ports P42, P43 and P5 are not included in the 7480 group. Fix each bit of the port P4P5 input control register to “0”. Fig. 10 Structure of pull-up control register I/O Ports [Direction Registers] The I/O ports have direction registers which determine the input/ output direction of each pin in units of bit. When a bit of the direc- tion register is set to “1”, the corresponding pin becomes an output port. When the bit is cleared to “0”, it becomes an input port. If data is read from a pin configured as output, the value of the port latch is read rather than the value of this pin. A pin configured as input becomes floating and its value can be read. If data is written to a pin, it is written to the port latch, but the pin remains floating. Fig. 11 Structure of port P4P5 input control register Port P4P5 input control register (P4P5CON : address 00D216) P42, P43 input control bit P5 input control bit (For the 7480 group) Set this bit to “0”. (For the 7481 group) Set this bit to “1”. b7 b0 Not used (“0” at read) Port P1 pull-up control register (P1PCON : address 00D116) P13 – P10 pull-up control bit P17 – P14 pull-up control bit b7 b0 Port P0 pull-up control register (P0PCON : address 00D016) P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit b7 b0 0 : Pull-up transistor OFF 1 : Pull-up transistor ON 0 : Pull-up transistor OFF 1 : Pull-up transistor ON Not used (undefined at read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 12 Block diagram of ports (1) Direction register Port latch Interrupt control circuit Tr1 Port P0 Data bus Port P0 Tr2 Port P13 Data bus T2M 1 Data bus Tr3 Port P12 Data bus T1M 1 Port P11 Tr4 Data bus Tr5 Data bus Port P10 Ports P10 – P13 Tr1 to Tr5 are pull-up transistors. Pull-up control register Port latch Pull-up control register Port latch Port latch Port latch Direction register Direction register Direction register Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 13 Block diagram of ports (2) Direction register Port latch Tr6 Port P17 Data bus SIOE SIOM SRDY SRDY Tr7 Port P16 Data bus SIOM SIOE SCLK output SCS SIOE Tr8 Port P15 Data bus SIOE TXD TE Tr9 Port P14 Data bus SIOE RE R XD Data bus Tr6 to Tr9 are pull-up transistors. Ports P14 – P17 SCLK input Direction register Port latch Direction register Port latch Direction register Port latch Pull-up control register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 14 Block diagram of ports (3) Data bus Multi- plexer Port P2 A-D conversion circuit Port P2 Port P3 INT0, INT1 Data bus Port P3 Data bus Port P40, P41 CNTR 0, CNTR 1 input Port P42, P43, P50, P51, P52, P53Data bus Port P42, P43, P50, P51, P52, P53 Timer output Timer X,Y operating mode bits “001” “100” “101” “110” Port P4 P5 input control register (For the 7480 group) Set this bit to “0”. (For the 7481 group) Set this bit to “1”. Port P40, P41 Direction register Port latch Direction register Port latch

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Interrupts Interrupts are vectored interrupts, and they can be caused by 14 different sources: 5 external sources, 8 internal sources, and 1 software source. (1) Interrupt Control All interrupts, except the BRK instruction interrupt, have an inter- rupt request bit and an interrupt enable bit. Additionally, a global interrupt disable flag affects them. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is ac- cepted. The interrupt request bits can be cleared by the program but can- not be set. The interrupt enable bit can be set and cleared by the program. The reset and BRK instruction interrupt can never be disabled. Other interrupts are disabled when the interrupt disable flag is set. (2) Interrupt Operation When an interrupt request is accepted: 1. The contents of the program counter and the processor status register are automatically pushed into the stack. 2. The interrupt disable flag is set and the interrupt request bit is cleared. 3. The interrupt jump destination address is read into the program counter. n Notes

• When the active edge of an external interrupt (INT 0, INT1, CNTR 0, CNTR1) is set, the interrupt request bit may also be set. Therefore, disable the external interrupt and set the edge polar- ity selection register. Then clear the interrupt request bit and accept the external interrupt.
• Input a trigger width over 250 ns to the INT 0/INT1 pin.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 4. Interrupt vector addresses and priority Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 :RESET is mentioned in the table because its operation is the same as an interrupt.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 16 Structure of registers related to interrupts b7 b0 Edge polarity selection register (EG : address 00D416) Interrupt control register 1 (ICON1: address 00FE16) b7 b0 Interrupt control register 2 (ICON2: address 00FF16) Interrupt request register 1 (IREQ1: address 00FC16) Interrupt request register 2 (IREQ2: address 00FD16) b7 b0 b7 b0b7 b0 Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Bus arbitration interrupt enable bit A-D conversion completion interrupt enable bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Bus arbitration interrupt request bit A-D conversion completion interrupt request bit INT0 interrupt enable bit INT1 interrupt enable bit CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enable INT0 interrupt request bit INT1 interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit 0 : No interrupt request 1 : Interrupt request INT0 selection bit 0 : Falling edge 1 : Rising edge INT1 selection bit 0 : Falling edge 1 : Rising edge CNTR 0 edge selection bit 0 : In event count mode, count rising edge. : In pulse output mode, start at “H” level output. : In pulse cycle measurement mode, measure a period from falling edge to falling edge. : In pulse width measurement mode, measure an “H” period. : In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” output. : Interrupt, falling edge active. 1 : In event count mode, count falling edge. : In pulse output mode, start at “L” level output. : In pulse cycle measurement mode, measure a period from rising edge to rising edge. : In pulse width measurement mode, measure an “L” period. : In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” level output. : Interrupt, rising edge active. CNTR 1 edge selection bit 0 : In event count mode, count rising edge. : In pulse output mode, start at “H” level output. : In pulse cycle measurement mode, measure a period from falling edge to falling edge. : In pulse width measurement mode, measure an “H” period. : In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” level output. : Interrupt, falling edge active. 1 : In event count mode, count falling edge. : In pulse output mode, start at “L” output. : In pulse cycle measurement mode, measure a period from rising edge to rising edge. : In pulse width measurement mode, measure an “L” period. : In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” output. : Interrupt rising edge active. INT 1 source selection bit at STP or WIT 0 : P31/INT1 1 : P00 – P07 “L” level (for key-on wake-up) Not used (undefined at read) Not used (undefined at read) 0 : Interrupt disabled 1 : Interrupt enabled 0 : No interrupt request 1 : Interrupt requested Not used (undefined at read) Not used (undefined at read) 0 : Interrupt disabled 1 : Interrupt enabled 0 : No interrupt request 1 : Interrupt requested

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Timers The 7480/7481 group has two 16-bit timers (timer X and timer Y), and two 8-bit timers (timer 1 and timer 2). All the timers are of a count-down type. When the timer reaches “FF 16” or “000016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt re- quest bit corresponding to this timer is set to “1”. At reading and setting the timer value to a 16-bit timer, be sure to read and set both high-order byte and low-order byte. At reading the count value from a 16-bit timer, read the high-order byte and the low-order byte in this order. At setting the count value in a 16-bit timer, set the low-order byte and the high-order byte in this order. The 16-bit timer cannot operate normally at reading during set op- eration or at setting during read operation. l Timer X, Timer Y Both timer X and timer Y are 16-bit timers independent from each other. They can select 7 operating modes by setting the mode registers. The registers related to timer X and timer Y are shown below. In the following, abbreviations will be used as register names.

• Timer XY control register (TXYCON: address 00F8 16)
• Port P4 direction register (P4D: address 00C916)
• Timer X low-order (TXL: address 00F016)
• Timer X high-order (TXH: address 00F116)
• Timer Y low-order (TYL: address 00F216)
• Timer Y high-order (TYH: address 00F316)
• Timer X mode register (TXM: address 00F616)
• Timer Y mode register (TYM: address 00F716)
• Edge polarity selection register (EG: address 00D416)
• Interrupt request register 1 (IREQ1: address 00FC16)
• Interrupt request register 2 (IREQ2: address 00FD16)
• Interrupt control register 1 (ICON1: address 00FE16)
• Interrupt control register 2 (ICON2: address 00FF16) For register structures, refer to each register structural diagram. In the following, each mode will be described. (1) Timer Mode/Event Count Mode À Timer Mode l Mode Selection This mode is selected by setting “000” in the timer X operating mode bits (b2b1b0) of TXM and the timer Y operating mode bits (b2b1b0) of TYM. l Count Source Selection The count source is f(X IN)/2, f(XIN)/8 or f(XIN)/16. l Interrupt When a timer underflows, the timer X interrupt request bit (b0) or timer Y interrupt request bit (b1) of IREQ1 is set to “1”. l Explanation of Operation After reset release, the timer X stop control bit (b0) or timer Y stop control bit (b1) of TXYCON is “1”, and the timer stops. In the timer stop status, usually the timer value is set by writing the latch and timer at the same time. Timer operation is started by setting “0” in b0 or b1 of TXYCON. When the timer reaches “0000 16”, an underflow occurs at the next count pulse, the corresponding timer latch is reloaded into the timer, and the count is continued. To change the timer value during count operation, the latch value is changed by writing to the latch only. At the next underflow reloading, the timer value is changed. \` Event Count Mode l Mode Selection Select the timer event count mode. This mode is selected by in- putting from the CNTR 0 pin for timer X or from the CNTR1 pin for timer Y (setting “11” in b7 and b6 of TXM or “11” in b7 and b6 of TYM). The count operation active edge is selected by setting in the CNTR0 edge selection bit (b2) or the CNTR1 edge selec- tion bit (b3) of EG. At “0”, the rising edge is counted. At “1”, the falling edge is counted. l Interrupt The underflow interrupt is the same as the timer mode. l Explanation of Operation This operation is the same as that of the timer mode. In this mode, set the port in common with the CNTR 0/CNTR 1 pin as an input port. Figure 19 shows a timing diagram in the timer event count mode. (2) Pulse Output Mode l Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “001”. l Count Source Selection The count source is f(X IN)/2, f(XIN)/8 or f(XIN)/16.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. same time. At writing only to the timer latch, when the write timing for the timer latch is almost equal to the underflow timing, the value that is set in the timer may not be constant. l Read Control for Timer X/Timer Y When the pulse cycle measurement mode or pulse width mea- surement mode is selected, the timer value cannot be read out. In the other modes, the timer value can be read regardless of count operation and count stop. However, the timer latch value cannot be read out. l Note on CNTR 0, CNTR1, INT0, INT1 Interrupt Polarity Selection When the CNTR 0/CNTR 1 edge selection bit or INT0/INT1 inter- rupt edge selection bit is set, this affects the respective interrupt polarity. n (n + m) (7) PWM Mode l Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “110”. l Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. l Interrupt At the rising edge of the CNTR0/CNTR 1 output, set the timer X interrupt request bit (b0) or timer Y interrupt request bit (b1) of IREQ1 to “1”. l Explanation of Operation In the case of timer X, the PWM waveform is output from the CNTR 0 pin. In the case of timer Y , the PWM waveform is output from the CNTR1 pin. The PWM waveform “H” period is determined by the setting value n (n=0 to 255) of TXH or TYH. The “L ” period is deter- mined by the setting value m (m=0 to 255) of TXL or TYL. The PWM cycle is as follows: PWM cycle = (n + m) 5 ts PWM output duty = ts: Timer X/timer Y count source cycle While a timer operation stops The timer value is set in TXL, TXH, TYL and TYH by writing to the timer and timer latch at the same time. The output of the CNTR 0/CNTR 1 pin is initialized to “H” by setting this timer value. While a timer operation is enabled When b1 and b0 of TXYCON are set to “0”, “H” is output during the period of the setting value of TXH or TYH. After that, “L ” is output during the period of the setting value of TXL or TYL. Then, these operations will be repeated. The PWM output sub- sequent to an underflow can be changed by setting the timer value in TXL, TXH, TYL, TYH by writing only to the timer latch. In this mode, set the port in common with the CNTR 0/CNTR 1 pin as an output port. n Note l When the PWM “H” period is set to “0016”, the PWM output is always “L” level. l When the PWM “L” period is set to “0016”, the PWM output is al- ways “H” level. l When the PWM “H” period is set to “0016” and the “L” period is set to “0016”, the PWM output is always “L” level. l When at least one of the PWM “H” period and “L” period is set to “00 16”, a timer X interrupt request/timer Y interrupt request does not occur. l When the timer latch is set at “0016”, the timer counts down, so its value is not constant. Figure 25 shows a timing diagram in the PWM mode. n Note on All Modes l Write Control for Timer X, Timer Y Timer X and timer Y can select either writing to both timer latch and timer or writing only to the timer latch by b3 of TXM or TYM. At writing only to the timer latch, a value is set in the timer latch by writing the value in the timer X/timer Y address, so the timer is updated at the next underflow. After reset release, writing to both the timer latch and timer is selected. At this status, when a value is written in the timer X/timer Y ad- dress, the value is set in both the timer and timer latch at the

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 17 Block diagram of timer X and timer Y PWM generating circuit D T Q Programmable one-shot output circuit T Q Q S Programmable waveform generation mode Pulse output mode CNTR 0 edge selection bit “1” “0” Programmable one-shot output mode PWM mode CNTR 0 edge selection bit Timer X (low-order) latch Timer X (high-order) latch Timer X (high-order) Timer X (low-order) Edge detecting circuit Timer X stop control bit Timer X count source selection bit Pulse width measurement mode Pulse cycle measurement mode CNTR 0 edge selection bit “001” “100” “101” “110” Timer X operating mode bits Programmable one-shot output mode PWM mode Output level latch P30/INT0 P40/CNTR 0 P40 direction register P40 latch f(XIN)/2 f(XIN)/8 f(XIN)/16 “1” “0” “1” “0” INT0 interrupt request Timer X interrupt request Pulse output mode D T Q Programmable one-shot output circuit T Q Q S Programmable waveform generation mode Pulse output mode CNTR 1 edge selection bit “1” “0” Programmable one-shot output mode PWM mode CNTR 1 edge selection bit Edge detecting circuit Timer Y count source selection bit “001” “100” “101” “110” Timer Y operating mode bits Programmable one-shot output mode PWM mode Output level latch P31/INT1 P41/CNTR 1 P41 direction register P41 latch f(XIN)/2 f(XIN)/8 f(XIN)/16 “1” “0” Pulse output mode Data bus “1” “0” Programmable waveform generation mode Timer X trigger selection bit Timer Y stop control bit D T Q “1” “0” Programmable waveform generation mode Timer Y trigger selection bit CNTR 1 edge selection bit “1” “0” “1” “0” INT0 edge selection bit “1” “0” INT1 edge selection bit Pulse width measurement mode Pulse cycle measurement mode PWM generating circuit Timer Y (low-order) latch Timer Y (high-order) latch Timer Y (high-order) Timer Y (low-order) CNTR 0 interrupt request INT1 interrupt request Timer Y interrupt request CNTR 1 interrupt request D T Q

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 18 Structure of timer X/timer Y mode register and timer XY control register Timer Y mode register (TYM : address 00F716) b7 b0 Timer X mode register (TXM : address 00F616) Timer XY control register (TXYCON : address 00F816) Not used (all “0” at read) b7 b0 b7 b0 Timer X stop control bit 0 : Count operation 1 : Count stop Timer Y stop control bit 0 : Count operation 1 : Count stop Timer X operating mode bits b2 b1 b0 0 0 0 : Timer event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse cycle measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not used Timer X write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Output level latch 0 : “L” output 1 : “H” output Timer X trigger selection bit 0 : Timer X free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT 0 pin) and timer X start in programmable waveform generation mode. Timer X count source selection bits b7 b6 00 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR0 pin Timer Y operating mode bits b2 b1 b0 0 0 0 : Timer event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse cycle measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not used Timer Y write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Output level latch 0 : “L” output 1 : “H” output Timer Y trigger selection bit 0 : Timer Y free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT1 pin) and timer Y start in programmable waveform generation mode. Timer Y count source selection bits b7 b6 0 0 : f(X IN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR1 pin

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 19 Timing diagram in timer mode/event count mode Fig. 20 Timing diagram in pulse output mode TR TR TR FFFF 16 TL 000016 TL : Value set in timer latch TR : Timer interrupt request TR TR TR FFFF 16 TL 000016 TL : Value set in timer latch TR : Timer interrupt request CNTR : CNTR 0/CNTR 1 interrupt request TR Output waveform from CNTR 0/CNTR 1 pin CNTR CNTR (CNTR polarity selection bit “0” : falling edge active)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 21 Timing diagram in pulse cycle measurement mode (at “rising edge interval” measurement) Fig. 22 Timing diagram in pulse width measurement mode (at “L section” measurement) TR FFFF 16 000016 TR : Timer interrupt request CNTR: CNTR 0/CNTR 1 interrupt request TR Input signal from CNTR 0/CNTR 1 pin CNTR CNTR CNTR CNTR FFFF 16+T1 T2 T3 FFFF 16 CNTR 0/CNTR 1 interrupt polarity is active at rising edge. TR FFFF 16 000016 TR : Timer interrupt request CNTR : CNTR 0/CNTR 1 interrupt request Input signal from CNTR 0/CNTR 1 pin CNTR CNTR CNTR FFFF 16+T2 T1 T3 CNTR 0/CNTR 1 interrupt polarity is active at rising edge, and pulse L width is measured.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 23 Timing diagram in programmable waveform generation mode (when trigger selection bit = “1”) Fig. 24 Timing diagram in programmable one-shot output mode TR FFFF 16 000016 L : Initial value of TLH , TLL TR : Timer interrupt request CNTR : CNTR 0/CNTR 1 interrupt request Output waveform from CNTR0/CNTR 1 pin L TR TR TR L T1 T2 Input signal from INT0/INT1 pin (CNTR polarity selection bit “0” : falling edge active) CNTR CNTR FFFF 16 000016 L : One-shot pulse width TR : Timer interrupt request CNTR : CNTR 0/CNTR 1 interrupt request Output waveform from CNTR CNTR 1 pin L TR TR TR L L L Input signal from INT0/INT1 pin (CNTR polarity selection bit “0” : falling edge active) CNTR CNTR CNTR

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 25 Timing diagram in PWM mode Timer X/timer Y count source Timer X/timer Y PWM output ts n5 t sm 5 t s (n+m)5 t s TR CNTR CNTR : CNTR 0/CNTR 1 interrupt request (CNTR polarity selection bit “0” : falling edge active) TR TR : Timer interrupt Note : A PWM waveform with duty n/(n+m) and cycle (n+m) 5 ts is output.

• TXH/TYH setting value: n= 0 – 255
• TXL/TYL setting value: m = 0 – 255
• Timer X/timer Y count source cycle: ts
• n+m = 0 – 510

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (1) Timer Mode The frequency of f(XIN)/8, f(XIN)/64, f(XIN)/128 or f(XIN)/256 is counted. (2) Programmable Waveform Generation Mode This operation is the same as the timer mode, except that a timer outputs the level of the value set in the output level latch of the timer 1 mode register/timer 2 mode register from the T 0 or T1 pin each time a timer underflows. After the timer underflows, the timer can output an optional wave- form from the T0 or T1 pin if the values of the output level latch and timer latch are changed. In this mode, set the port in common with the T0/T1 pin as an out- put port. Fig. 26 Block diagram of timer 1, timer 2 l Timers 1 and 2 Timer 1 and timer 2 are the 8-bit timers. They can select the fol- lowing 2 modes by setting timer 1 mode register and timer 2 mode register.

• Timer mode
• Programmable waveform generation mode When the count source is changed, set it again as the timer value may go wrong. Fig. 27 Structure of timer 1/timer 2 mode register Timer stop control bit 0 : Count operation 1 : Count stop Timer 1 mode register (T1M : address 00F916) Timer 2 mode register (T2M : address 00FA16) b7 b0 Timer operation mode bit 0 : Timer mode 1 : Programmable waveform generation mode Output level latch 0 : “L” output 1 : “H” output Timer count source selection bits b7 b6 0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256 Not used (“0” at read) Not used (“0” at read) Timer mode register Count stop control bitf(XIN)/8 Timer interrupt request bit T TL Data bus Data bus f(XIN)/64 f(XIN)/128 f(XIN)/256 Output level latch T DQ Timer count source selection bits “00” “01” “10” “11” T0, T1 output

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. the serial I/O mode selection bit of the serial I/O control register (address 00E216) to “1”. In the clock synchronous serial I/O, the transmitter-side microcom- puter and the receiver-side microcomputer must use the same clock for serial I/O operation. If an internal clock is used as oper- ating clock, a transfer is started by a write signal to the transmit/ receive buffer register. Fig. 28 Block diagram of clock synchronous serial I/O Fig. 29 Operation of clock synchronous serial I/O function Data bus Data bus Receive buffer register Clock control circuit Serial I/O control register Falling edge detection Serial I/O status register F/F 1/4 1/4 Transmit shift register shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O synchronous clock selection bit (SCS) Frequency division ratio 1/(n+1) P16 P14 Shift clock P15P17 Clock control circuit Receive shift register Transmit shift register Transmit buffer register TXD SRDY SCLK R XD XIN SRDY output enable bit (SRDY) Address 00E016 Address 00E216 Address 00E016 Address 00E116 Address 00E416 BRG count source selection bit (CSS) Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O enable bit (SIOE) Baud rate generator Serial I/O Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O is in opera- tion. (1) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode can be selected by setting D 0 D 1 D 2 D3 D 4 D 5 D 6 D7 D 0 D 1 D 2 D3 D 4 D 5 D 6 D7 TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Transmit/receive shift clock, 1/8 – 1/8192 of internal clock, or external clock Serial output TxD Serial input RxD Receive enable signal SRDY Write signal to receive/ transmit buffer register (address 00E016) Notes 1 : The transmit interrupt (TI) can be selected to be generated either when the transmit buffer is empty (TBE = 1) or after the transmit shift operation is completed (TSC = 1) by using the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC = 0, the transmit clock is generated continuously, and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Each of the transmit and receive registers has a buffer register (the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the trans- mit buffer register and receive data is read from the receive buffer register. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. (2) Asynchronous Serial I/O (UART) Mode The UART mode can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identi- cal. Fig. 30 Block diagram of UART serial I/O Fig. 31 Operation of UART serial I/O function Receive buffer register Clock control circuit Serial I/O control register Baud rate generator Serial I/O status register Transmit shift register shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Receive interrupt request (RI) Frequency division ratio 1/(n+1) P14 P15P16 Receive shift register Transmit shift register Transmit buffer register TXD SCLK R XD XIN Address 00E016 Address 00E216 Address 00E016 Address 00E116 Address 00E416 7-bit UART control register ST/SP/PA generation Serial I/O synchronous clock selection bit (SCS) OE SP detection8-bit PE FE ST detection Address 00E316 Receive enable bit (RE) Transmit enable bit (TE) Character length selection bit (CHAS) Character length selection bit (CHAS) BRG count source selection bit (CSS) Data bus Data bus Serial I/O enable bit (SIOE) Serial I/O synchronous clock selection bit (SCS) Transmit interrupt source selection bit (TIC) ST D 0 D 1 SP ST D 0 D 1 SP Transmit or receive clock Transmit buffer register write signal Serial output TxD Receive buffer register read signal Serial input RxD TBE=0 TSC=0 TBE=0 TBE=1 RBF=0 RBF=1 RBF=1 TSC=1 1 start bit 7/8 data bit 1/0 parity bit 1/2 stop bit ST D 0 D 1 SP ST D 1 SP ]Generated at 2nd bit in 2 stop bit mode Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception). 2 : The transmit interrupt (TI) can be selected to be generated when either TBE=1 or TSC=1, depending on the setting of the transmit interrupt source selection bit of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. D 0 TBE=1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. b7 b0UART control register UARTCON (address 00E316) Character length selection bit (CHAS) 0 : 8-bit 1 : 7-bit Not used (“1” at read) Parity enable bit (PARE) 0 : Parity disabled 1 : Parity enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits b7 b0Serial I/O control register SIOCON (address 00E216) BRG count source selection bit (CSS) 0 : f(XIN)/4 1 : f(XIN)/16 Serial I/O synchronous clock selection bit (SCS) 0 : BRG output/4 (when clock synchronous serial I/O is selected) BRG output/16 (when UART is selected) 1 : External clock input (when clock synchronous serial I/O is selected) External clock input/16 (when UART is selected) SRDY output enable bit (SRDY) 0 : P17 pin operates as ordinary I/O pin. 1 : P17 pin operates as SRDY output pin. Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer is empty. 1 : Interrupt when transmit shift operation is completed. Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (P1 4 to P17: ordinary I/O ports) 1 : Serial I/O enabled (P14 to P17: serial I/O function pins) b7 b0 Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift register shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE)U(PE)U(FE)=0 1 : (OE)U(PE)U(FE)=1 Not used (“1” at read) Serial I/O status register SIOSTS (address 00E116) [Serial I/O Control Register] SIOCON The serial I/O control register consists of 8 control bits for control of the serial I/O. [UART Control Register] UARTCON The UART control register is a 4-bit control register which is valid when UART is selected. This 4-bit control register sets a data for- mat for serial data transfer. [Serial I/O Status Register] SIOSTS This is a 7-bit read-only register consisting of flags that indicate the serial I/O operating status and different error flags. The 3 bits of bit 4 to bit 6 are valid only in the UART mode. The receive buffer full flag is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. Writing to the serial I/O status register clears all the error flags (OE, PE, FE, SE). All the bits of this register are initialized to “0” at reset. However, if the transmit enable bit of the serial I/O control register is set to “1”, bit 2 and bit 0 become “1”. [Transmit Buffer Register/Receive Buffer Register] TB/RG The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is a write-only type and the receive buffer register is a read-only type. If a character bit length is 7 bits, the MSB of the receive data stored in the receive buffer is “0”. [Baud Rate Generator] BRG The baud rate generator determines a baud rate for serial transfer. The baud rate generator, being an 8-bit counter with a reload reg- ister, divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. Fig. 32Structure of serial I/O related registers (SIOSTS, UARTCON, SIOCON)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. group serial I/O Interface driver/ receiver TxD RxD LAN data bus Bus Arbitration Interrupt The 7480/7481 group is provided with a built-in bus arbitration in- terrupt as a function for bus conflict system communication. At such bus conflict system communication, as shown in Figure 33, if transmit data cannot be transmitted to the LAN data bus due to a transmit data collision, the data collision can be detected by the bus arbitration interrupt. Fig. 33 Example of bus conflict system communication

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A transmit data collision is detected between LSB and MSB of transmit data in the clock synchronous serial I/O mode or between the start bit and stop bit of transmit data in the UART mode. Bus collision detection can be performed by both the internal clock and the external clock. A block diagram is shown in Figure 34. A timing diagram is shown in Figure 35. A bus collision detection control register is shown in Figure 36. Fig. 34 Block diagram of bus arbitration interrupt circuit Fig. 36 Structure of bus collision detection control register TXD R XD Shift clock D Q Bus arbitration interrupt request Bus collision detection enable bit TE Transmit shift clock Transmit pin TxD Receive pin RxD Bus arbitration interrup t generation Data collision Bus Collision Detection The 7480/7481 group can detect a bus collision by setting the bus collision detection enable bit to “1”. When transmission is started in the clock synchronous or asyn- chronous (UART) serial I/O mode, the transmit pin TxD is compared with the receive pin RxD in synchronization with a rising edge of transmit shift clock. If they do not coincide with each other, a bus arbitration interrupt request occurs (bus collision detection). Fig. 35 Timing diagram of bus arbitration interrupt b7 b0 Bus collision detection control register (BUSARBCON address 00E5 16) Bus collision detection enable bit 0 : Collision detection disabled 1 : Collision detection enabled Not used (“0” at read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 37 Priority control at simplified SAEJ1850 BUS+ BUS- Unit A Unit B Unit A LAN data bus Unit B Continue to transmit Stop transmitting Data collision LAN data bus Application Example Priority Control at Simplified SAEJ1850 At simplified SAEJ1850 communication, when multiple units start to transmit data at the same time, priority control is exerted. On the LAN data bus, the “H” level has priority over the “L” level. When an “H” level collides with an “L” level, the LAN data bus sta- tus goes to the “H” level. For example, when unit A outputs “H” and unit B outputs “L ” at the same time in Figure 37, the LAN data bus goes to “H”. Accord- ingly, unit A takes priority of control and continues its transmission, and unit B stops its transmission immediately. In this way, the 7480/7481 group exerts priority control for each bit and finally allows only the highest-priority unit to transmit data.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A-D Converter For A-D conversion, the 8-bit successive comparison method is used. Figure 38 shows a block diagram of A-D conversion. Con- version is automatically performed once started by the program. There are 8 analog input pins that are in common with P2 7 to P20 of port P2 (4 pins of P23 to P20 in the 7480 group). Pin inputs to be A-D converted are selected by bit 2 to bit 0 of the A-D control register (address 00D9 16). Bit 3 of the A-D control reg- ister is an A-D conversion completion bit. This bit is “0” during A-D conversion and “1” after completion of it. Accordingly, it is possible by checking this bit to know whether A-D conversion is completed or not. Figure 39 shows the relationship between the contents of the A-D control register and input pins to be selected. The A-D conversion register (address 00DA 16) stores conversion results, so it is possible to know them by reading the contents of this register. Next, the procedure for executing A-D conversion will be ex- plained below. First, set values in bit 2 to bit 0 of the A-D control register and select pins to be A-D converted. Next, clear the A-D conversion completion bit to “0”. With this write operation, A-D conversion is started. The A-D conversion is com- pleted after the lapse of 50 machine cycles (12.5 µs at f(XIN)= 8 MHz), and the A-D conversion completion bit is set to “1”. The A-D conversion interrupt request bit is also set to “1”. Conversion re- sults are stored in the A-D conversion register. Fig. 38 Block diagram of A-D converter circuit Comparator A-D control circuit A-D conversion register (address 00DA16) Switch tree Ladder resistor A-D conversion completion interrupt request VSS (Note 1) VREF 1 : AVSS for the 44P6N package of the 7481 group. 2 : The 7480 group is not provided with P24/IN4 to P27/IN7. P20/IN0 P21/IN1 P22/IN2 P23/IN3 P24/IN4 P25/IN5 P26/IN6 P27/IN7 Data bus A-D control register (address 00D916) b4 b0 Channel selector Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 39 Structure of A-D control register A-D control register ADCON (address 00D916) Analog input pin selection bits 000 : P20/IN0 001 : P21/IN1 010 : P22/IN2 011 : P23/IN3 100 : P24/IN4 101 : P25/IN5 110 : P26/IN6 111 : P27/IN7 A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF connection selection bit 0: Disconnect between VREF pin and ladder resistor 1: Connect between VREF pin and ladder resistor b7 b0 Note : Do not perform setting in the 7480 group. (Note) Not used (undefined at read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of a 7-bit watchdog timer L and an 8- bit watchdog timer H. l Initial Value of Watchdog Timer By a reset or writing to the watchdog timer H, the watchdog timer H is set to “FF 16” and the watchdog timer L is set to “7F16”. Any in- struction that permits generating a write signal can be used; for example, STA, LDM, CLB, etc. Write data has no significance, so the above values are set regardless of that data. l Operation of Watchdog Timer The watchdog timer stops at reset, and writing a value in the watchdog timer H causes it to start to count down. When bit 7 of the watchdog timer H becomes “0”, an internal reset occurs. The reset status is released as soon as the release reset time is up. After that, the 7480/7481 group runs the program from the re- set vector address. It is programmed that the watchdog timer H can be set before bit 7 of the watchdog timer H is cleared to “0”. If the watchdog timer H is never written, the watchdog timer does not function. When the STP instruction is executed, the clock stops and the watchdog timer also stops. The count is restarted as soon as the stop mode is released. (Note) On the other hand, the watchdog timer does not stop after execution of the WIT instruc- tion. The timing from writing to the watchdog timer H to clearing bit 7 of the watchdog timer H to “0” is shown below. (f(X IN)=8 MHz) Note:Since the watchdog timer still counts for the stop release waiting time (about 2048 cycles of X IN), bit 7 of the watch- dog timer H should not be cleared to “0” in this period. Fig. 40 Block diagram of watchdog timer Watchdog timer L (7) Watchdog timer H (8) “0” “1” Watchdog timer L count source selection bit Write “7F16” to the watchdog timer register Write “FF16” to the watchdog timer register Data bus Reset circuit Internal reset RESET f(XIN) bit7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. STP/WIT Instruction Control The STP instruction and the WIT instruction can be enabled or disabled selectively by using the STP instruction operation control register. T o cope with a program runaway after reset, the STP in- struction and the WIT instruction are disabled in the initial status. The STP and WIT instructions can be set as enable/disable only by writing to the STP instruction operation control register twice successively so as not to stop the oscillation clock even if a write data error is caused by program runaway. Figure 41 shows a structure of the STP instruction operation control register. Fig. 41 Structure of STP instruction operation control register Explanation of STP Instruction Operation Control Register The STP instruction operation control register will be enabled by writing data to the same address twice successively. If data is not written in continuous form, the written data is not valid but the pre- vious value is held. If an interrupt is received while the same data is written twice, there is a possibility that the write instruction in the interrupt rou- tine may be executed. For this reason, rewriting is required after interrupt disable. Figure 42 shows a reference example of data re- writing. Fig. 42 Reference example of data rewriting b7 b0 STP instruction operation control register (STPCON: address 00DE16) STP instruction and WIT instruction enable/disable selection bit (Note) 0 : STP/WIT instruction enabled 1 : STP/WIT instruction disabled Not used (“0” at read) The STP instruction and the WIT instruction are disabled in the initial status. When using these instructions, set bit 0 of the STP instruction operation control register to “1”, then set this bit to “0”. (Writing twice successively) When not using the STP and WIT instructions, set this bit to “1” either once or twice. Note : l STP/WIT instruction enable SEI LDM #01H, 0DEH LDM #00H, 0DEH CLI Use only in interrupt enable status Interrupt disable in this period l STP/WIT instruction disable SEI LDM #01H, 0DEH LDM #01H, 0DEH CLI Use only in interrupt enable status Interrupt disable in this period

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Recovery From Power-down Status By Key Input Interrupt (Key-on wake-up) “Key-on wake-up” is one way of recovery from a power-down sta- tus by using the STP or WIT instruction. If an “L” level voltage is input to any pin of port P0 when bit 5 of the edge polarity selection register is “1”, an interrupt occurs, and a recovery can be made to the normal operating state. If a key matrix of active “L” with port P0 as an input port is constructed, a recovery can be made to the normal operating status by pressing a key. The key input interrupt is in common with the INT 1 interrupt. When bit 5 of the edge polarity selection register is set to “1”, the key in- put interrupt function is selected. If this bit is set to “1” except in the power-down status, both INT1 and key-on wake-up are invali- dated. Fig. 43 Block diagram of interrupt input/key-on wake-up circuit P41/CNTR 1 P40/CNTR 0 P30/INT0 P31/INT1 P07 P01 EG 3 Port P41 data read circuit CNTR 1 interrupt request signal Port P40 data read circuit EG 0 Port P30 data read circuit INT0 interrupt request signal Port P31 data read circuit INT1 interrupt request signal CPU stop status signal Port P0 data read circuit EG 1 EG 5 P00 EG 2 CNTR 0 interrupt request signal Pull-up control register Direction register Pull-up control register Direction register Pull-up control register Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Clock Generating Circuit The 7480/7481 group is provided with a built-in oscillation circuit. An oscillation circuit can be formed by connecting a resonator be- tween X IN and XOUT . Use the manufacturer's recommended values for constants such as capacitance, which will differ de- pending on each resonator. The 7480/7481 group has a built-in feedback resistor between the X IN and XOUT pins, so an external resistor can be omitted. l Frequency Control (1) High-speed Mode The frequency applied to the clock input pin XIN divided by 2 is used as the internal clock φ. This mode is set after reset release. (2) Medium-speed Mode The frequency applied to the clock input pin X IN divided by 8 is used as the internal clock φ. l Oscillation Frequency (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and the oscillator stops. At this time, timer 1 is set to “FF16,” and f(XIN)/8 is forcibly connected to the count source of timer 1. Accordingly, set the timer 1 interrupt enable bit to the dis- able status (“0”) before execution of the STP instruction. When a reset or an external interrupt is accepted, oscillation is re- started, but the internal clock φ is supplied to the CPU after timer 1 underflows. This is because when an external resonator is used, some time is required until a start of oscillation. (2) Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. But, the oscillator does not stop. When a reset or inter- rupt is accepted, the stop status is released. The microcomputer can execute any instruction immediately, because the oscillator does not stop. Fig. 44 External circuit of ceramic resonator Fig. 45 External clock input circuit XIN XOUT C OUTC IN R d XIN XOUT External oscillation circuit Open VCC VSS Duty ratio 50%

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 46 Block diagram of clock generating circuit Q R S Q R SQ R SQ R SQ R S XIN XOUT 1/2 1/4 Timer 1 Reset STP instruction Reset Interrupt disable flag Interrupt request STP instruction WIT instruction Internal clock “1” “0” CM 6

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Reset Circuit The microcomputer is put into a reset status by holding the_____ RESET pin at the “L” level for 2µs or more when the power source voltage is 2.7 to 5.5 V and XIN is in stable oscillation._____ After that, this reset status is released by returning the RESET pin to the “H” level. The program starts from the address having the contents of address FFFF 16 as high-order address and the con- tents of address FFFE16 as low-order address. Note that the reset input voltage should be 0.32 V or less when the power source voltage passes 2.7 V. Fig. 47 Reset circuit diagram Fig. 48 Reset sequence RESET V CC RESET V CC Power source voltage Reset input voltage 0.12VCC Power ON (Note) Note : Reset release voltage VCC = 2.7 V Power source voltage detecting circuit ? ?? ? FFFE 16 FFFF 16 AD H,L ?? ? ? A D L AD H XIN f RESET Internal reset Address Data SYNC X IN 2048 clock cycle Reset address from the vector table Notes 1 : The frequency relation between f(XIN) and is f(XIN)=2·f( ). 2 : The mark “?” means that the address is changeable depending on the previous state. ff

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 49 Internal state of microcomputer at reset : At reset release, the read value is undefined. 0000 Contents of address FFFF16 Address ( 1 ) Port P0 direction register (P0D) (C116) • • • Contents of address FFFE16 ( 2 ) Port P1 direction register (P1D) (C316) • • • ( 4 ) Port P5 direction register (P5D) (CB16) • • • ( 5 ) Port P0 pull-up control register (P0PCON) (D016) • • • ( 6 ) Port P1 pull-up control register (P1PCON) (D116) • • • ( 8 ) Edge polarity selection register (EG) (D416) • • • ( 9 ) A-D control register (ADCON) (D916) • • • (22) Timer Y mode register (TYM) (F716) • • • (23) Timer XY control register (TXYCON) (F816) • • • (24) Timer 1 mode register (T1M) (F916) • • • (25) Timer 2 mode register (T2M) (FA16) • • • (26) CPU mode register (CPUM) (FB16) • • • (27) Interrupt request register 1 (IREQ1) (FC16) • • • (28) Interrupt request register 2 (IREQ2) (FD16) • • • (29) Interrupt control register 1 (ICON1) (FE16) • • • (30) Interrupt control register 2 (ICON2) (FF16) • • • (31) Program counter (PCH ) (32) Processor status register (PS) ( 3 ) 16) • • • (10) STP instruction operation control register (STPCON)(DE16) • • • (11) Serial I/O status register (SIOSTS) (E116) • • • (12) Serial I/O control register (SIOCON) (E216) • • • (13) UART control register (UARTCON) (E316) • • • (15) Watchdog timer H (WDTH) (EF16) • • • (21) Timer X mode register (TXM) (F616) • • • (PCL) 00000 010 00001 1 11 ( 7 ) Port P4P5 input control register (P4P5CON) (D216) • • • (14) Bus collision detection control register (BUSARBCON)(E516) • • • 0000 FF16 100 00000 11000000 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (19) Timer Y high-order (TYH) (F316) • • • FF16 FF16 (18) Timer Y low-order (TYL) (F216) • • • (17) Timer X high-order (TXH) (F116) • • • FF16 FF16 (16) Timer X low-order (TXL) (F016) • • • FF16 0016 00000 10000 Note : Some kinds of microcomputers do not use some of these bits. Refer to the structure of each register. 0000 0 0000 0000 b7 b0 Port P4 direction register (P4D) (C9

Notice: This is not a final specification. Some parametric limits are subject to change. Table 5. Pin description Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS and AVSS . Reference voltage input pin for A-D converter. nected between XIN and XOUT . 8-bit I/O port. The output structure is CMOS output. nected in units of 1 bit, and a key-on wake-up function is provided. 8-bit I/O port. The output structure is CMOS output. serial I/O pins RxD, TxD, SCLK and SRDY . P11 to P17 are address (A4 to A10) input pins. Leave P10 open. IN7 (IN0 to IN3 for the 7480 group). having a built-in clamp diode. Notes 1 : This is a dedicated pin for the 44P6N-A package in the 7481 group. 2 :Only 4 bits of P20 to P23 (IN0 to IN3) for the 7480 group. 3 :Only 2 bits of P40 and P41 for the 7480 group. 4 :This is a dedicated pin for the 7481 group.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 6. Correspondence between pins in EPROM mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 51 Pin connection in EPROM mode (2) Fig. 52 Pin connection in EPROM mode (3) Outline 44P6N-A : PROM pin (equivalent to M5M27C256K) P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P20/IN0 V REF X IN X OUT V SS AV SS P30/INT0 RESET V CC P51 P50 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P43 P42 P07 P06 P05 P04 P52 P17/SRDY P16/SCLK P15/TXD P14/RXD P53 VSS M37481E8-XXXFP M37481E8T-XXXFP P03 A14 A13 VPP A12 D 2 D 1 D 0 OE D 3 D 4 D 5 D 6 D 7 VSS A10 A11 VSS VCC VSS CE A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : PROM pin (equivalent to M5M27C256K) 16 17 M37480E8-XXXSP/FP M37480E8T-XXXSP/FP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET V CC Outline 32P4B 32P2W-A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. The screening temperature is up to 150°C. Never expose to 150°C exceeding 100 hours. The M37480E8SP/FP, M37481E8SP/FP and M37481E8SS are not T versions (mountable on vehicles), so it is impossible to mount them on vehicles. The M37481E8SS is for user program evaluation, so it is impossible to mount it on vehicles or on user’s mass-production real machines. Writing with PROM programmer Screening (Leave at 150°C for 40 hours.) (Note) Verify test with PROM programmer Function check in target device Note : FUNCTIONAL DESCRIPTION OF PROM VERSION Reading __ __ To read the PROM, set the CE and OE pins to “L ” level, and set the address signal (A0 to A14). The stored contents will appear to__ __ data I/O pins (D0 to D7). When the CE and OE pins are set to “H” level, the data I/O pins will be put into a floating status. Writing __ To write to the PROM, apply “H” to the OE pin and VPP to the VPP pin to set the program mode. Select addresses to be written to with address input pins (A0 to A14) and give write data to the data input pins (D0 to D7) in 8-bit parallel form. In this status, when the__ CE pin becomes “L”, writing will be started. Notes on Writing When using a PROM programmer, specify the address range to address 4000 16 to address 7FFF16. When data is written between address 000016 and address 7FFF 16, fill addresses 000016 to 3FFF16 with “FF16”. Erasing Data can be erased only on the ceramic package with window M37481E8SS. To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power required for erasing is 15W·s/cm NOTES ON HANDLING (1) Sunlight and fluorescent light contain wavelengths capable of erasing data. For use in the read mode, be sure to cover the transparent window with a seal. (Ceramic package type) (2) We can supply the seal with which the transparent window is covered. Be careful not to allow the seal to contact the micro- computer lead pins. (Ceramic package type) (3) Before erasing, clean the transparent glass. If the glass is smeared with greasy hands or paste, ultraviolet light transmis- sion will be prevented, having a negative effect on erasing characteristics. (Ceramic package type) (4) Since a high voltage is used for writing data, care should be taken not to apply an overvoltage when turning on the power source. (5) For the programmable microcomputers (one-time program- mable version, version shipped in blank), Mitsubishi does not perform PROM write testing and screening in the assembly process and subsequent processes. To improve reliability after writing, perform writing and testing according to the following operation flow before use. Fig. 53 Writing and testing for one-time programmable version

Notice: This is not a final specification. Some parametric limits are subject to change. Table 7. I/O signals in each mode Note : VIL and VIH denote an “L ” input voltage and an “H” input voltage, respectively.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tents of the processor status register. DATA REQUIRED FOR MASK ORDERING Please submit the following data when placing mask orders. (1) Mask ROM confirmation form (2) Mark specification form DATA REQUIRED FOR ROM WRITING ORDERING Please submit the following data when placing ROM writing or- ders. (1) ROM writing confirmation form (2) Mark specification form ADDRESSING MODES The 7480/7481 group has strong accessability, because it has 17 kinds of addressing modes. For details, refer to the 740 family ad- dressing modes. MACHINE-LANGUAGE INSTRUCTIONS The 7480/7481 group has 71 machine-language instructions. For details, refer to the 740 family machine-language instruction list. NOTES ON PROGRAMMING (1) The frequency division ratio of the timer is 1/(n+1). n: Timer setting value However, n = 0 – 255 (for timer 1, timer 2) n = 0 – 65535 (timer X, timer Y) (2) The contents of the interrupt request bits can be changed by software, but the values will not change immediately after be- ing overwritten. After changing the value of the interrupt request bits, execute at least one instruction before executing a the BBC or BBS in- struction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD in- struction. (4) A NOP instruction should be executed after every PLP instruc- tion. (5) Do not execute the STP instruction during A-D conversion. (6) Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instructions. The execution of these instructions does not change the con-

Notice: This is not a final specification. Some parametric limits are subject to change. Table 8. Absolute maximum ratings Output transistors are cut off. Notes 1 :500 mW for 32P2W-A package type. 2 :–40 to 85 °C for extended operating temperature range version. 3 :–65 to 150 °C for extended operating temperature range version. Table 9. Recommended operating conditions

0.7 VCC

0.8 VCC

0.9 VCC

0.2 VCC

0.25 VCC

0.4 VCC

0.3 VCC

0.16 VCC

0.12 VCC

Notice: This is not a final specification. Some parametric limits are subject to change. Table 9. Recommended operating conditions (cont.) Notes 1 :–40 to 85 °C for extended operating temperature range version. 2 :The average output currents IOH (avg) and IOL (avg) are the average values during 100 ms. 3 :The clock input oscillation frequency is at 50 % duty ratio. 4 :When applying a voltage through a resistor as shown in the figure 54, VI > VCC may be accepted if the current is 1 mA or less. raise the power source pin voltage of the microcomputer. sudden stress, such as rush current, directly to the diode. using a relatively thick wire. P33/VPP pin the shortest possible in series.

Notice: This is not a final specification. Some parametric limits are subject to change. Notes 1 :–40 to 85 °C for extended operating temperature range version. 2 :At using P0 for key-on wake-up function. Table 10. Electrical characteristics

Notice: This is not a final specification. Some parametric limits are subject to change. Table 10. Electrical characteristics (cont.)

Notice: This is not a final specification. Some parametric limits are subject to change. Table 11. A-D conversion characteristics

0.5 VCC

Note: –40 to 85 °C for extended operating temperature range version.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 12. Absolute maximum ratings Output transistors are cut off. Notes 1 :500 mW for 44P6N-A package type. 2 :–40 to 85 °C for extended operating temperature range version. 3 :–65 to 150 °C for extended operating temperature range version. Table 13. Recommended operating conditions

Notice: This is not a final specification. Some parametric limits are subject to change. Table 13. Recommended operating conditions (cont.) Notes 1 :–40 to 85 °C for extended operating temperature range version. 2 :The average output currents IOH (avg) and IOL (avg) are the average values during 100 ms. 3 :The clock input oscillation frequency is at 50 % duty ratio. 4 :When applying a voltage through a resistor as shown in the figure 55, VI > VCC may be accepted if the current is 1 mA or less. sudden stress, such as rush current, directly to the diode. using a relatively thick wire. P33/VPP pin the shortest possible in series.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 14. Electrical characteristics Notes 1 :–40 to 85 °C for extended operating temperature range version. 2 :Using P0 for key-on wake-up function.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 14. Electrical characteristics (cont.)

Notice: This is not a final specification. Some parametric limits are subject to change. Note: –40 to 85 °C for extended operating temperature range version. Table 15. A-D conversion characteristics

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Receipt Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor M37480M2T-XXXSP GZZ-SH09-84B<56A0>

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : 27128 27256 000016 000F16 001016 2FFF16 300016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M2T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M2T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 0000 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37480M2T-XXXFP 27512 000016 000F16 001016 6FFF16 700016 7FFF16 EPROM address 000016 000F16 001016 EFFF16 F00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480M2T–’ Area for ASCII codes of the name of the product ‘M37480M2T-’ Area for ASCII codes of the name of the product ‘M37480M2T–’ ROM (4K) ROM (4K) ROM (4K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. MASK ROM CONFIRMATION FORM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-84B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M2T-XXXSP, 32P2W-A for M37480M2T-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37480M2T–’ ]= $0000 .BYTE ‘M37480M2T–’ 27128 ]= $C000 .BYTE ‘M37480M2T–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37480M4-XXXSP GZZ-SH09-85B<56A0> SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37480M4-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480M4–’ Area for ASCII codes of the name of the product ‘M37480M4-’ Area for ASCII codes of the name of the product ‘M37480M4–’ ROM (8K) ROM (8K) ROM (8K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-85B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4-XXXSP, 32P2W-A for M37480M4-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37480M4–’ ]= $0000 .BYTE ‘M37480M4–’ 27128 ]= $C000 .BYTE ‘M37480M4–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37480M4T-XXXSP GZZ-SH09-86B<56A0> SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M4T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M4T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37480M4T-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480M4T–’ Area for ASCII codes of the name of the product ‘M37480M4T-’ Area for ASCII codes of the name of the product ‘M37480M4T–’ ROM (8K) ROM (8K) ROM (8K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-86B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4T-XXXSP, 32P2W-A for M37480M4T-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37480M4T–’ ]= $0000 .BYTE ‘M37480M4T–’ 27128 ]= $C000 .BYTE ‘M37480M4T–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37480M8-XXXSP GZZ-SH09-87B<56A0> SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37480M8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480M8–’ Area for ASCII codes of the name of the product ‘M37480M8–’ ROM (16K) ROM (16K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37480M8-’ ]= $0000 .BYTE ‘M37480M8-’ SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-87B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8-XXXSP, 32P2W-A for M37480M8-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37480M8T-XXXSP GZZ-SH09-88B<56A0> SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M8T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37480M8T-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480M8T–’ Area for ASCII codes of the name of the product ‘M37480M8T–’ ROM (16K) ROM (16K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37480M8T-’ ]= $0000 .BYTE ‘M37480M8T-’ SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-88B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8T-XXXSP, 32P2W-A for M37480M8T-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481M2T-XXXSP GZZ-SH09-78B<56A0> SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : 27128 27256 000016 000F16 001016 2FFF16 300016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M2T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M2T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37481M2T-XXXFP 27512 000016 000F16 001016 6FFF16 700016 7FFF16 EPROM address 000016 000F16 001016 EFFF16 F00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481M2T–’ Area for ASCII codes of the name of the product ‘M37481M2T-’ Area for ASCII codes of the name of the product ‘M37481M2T–’ ROM (4K) ROM (4K) ROM (4K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-78B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M2T-XXXSP, 44P6N-A for M37481M2T-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37481M2T–’ ]= $0000 .BYTE ‘M37481M2T–’ 27128 ]= $C000 .BYTE ‘M37481M2T–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481M4-XXXSP GZZ-SH09-79B<56A0> SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M4–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37481M4-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481M4–’ Area for ASCII codes of the name of the product ‘M37481M4-’ Area for ASCII codes of the name of the product ‘M37481M4–’ ROM (8K) ROM (8K) ROM (8K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-79B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4-XXXSP, 44P6N-A for M37481M4-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37481M4–’ ]= $0000 .BYTE ‘M37481M4–’ 27128 ]= $C000 .BYTE ‘M37481M4–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481M4T-XXXSP GZZ-SH09-80B<56A0> Microcomputer name : 27128 27256 000016 000F16 001016 1FFF16 200016 3FFF16 Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M4T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M4T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM address EPROM type (indicate the type used) Microcomputer name : M37481M4T-XXXFP 27512 000016 000F16 001016 5FFF16 600016 7FFF16 EPROM address 000016 000F16 001016 DFFF16 E00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481M4T–’ Area for ASCII codes of the name of the product ‘M37481M4T-’ Area for ASCII codes of the name of the product ‘M37481M4T–’ ROM (8K) ROM (8K) ROM (8K) SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-80B<56A0> Recommend to writing the following pseudo-command to the start address of the assembler source program. Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4T-XXXSP, 44P6N-A for M37481M4T-XXXFP) and attach to the mask ROM confirmation form. 27256 27512 ]= $8000 .BYTE ‘M37481M4T–’ ]= $0000 .BYTE ‘M37481M4T–’ 27128 ]= $C000 .BYTE ‘M37481M4T–’ EPROM type The pseudo-command h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481M8-XXXSP GZZ-SH09-81B<56A0> SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37481M8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481M8–’ Area for ASCII codes of the name of the product ‘M37481M8–’ ROM (16K) ROM (16K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37481M8-’ ]= $0000 .BYTE ‘M37481M8-’ SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-81B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8-XXXSP, 44P6N-A for M37481M8-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments Mask ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481M8T-XXXSP GZZ-SH09-82B<56A0> SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M8T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37481M8T-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481M8T–’ Area for ASCII codes of the name of the product ‘M37481M8T–’ ROM (16K) ROM (16K) Mask ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37481M8T-’ ]= $0000 .BYTE ‘M37481M8T-’ SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-82B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8T-XXXSP, 44P6N-A for M37481M8T-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments Mask ROM number

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Receipt Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor M37480E8-XXXSP GZZ-SH09-91B<56A0>

740 FAMILY ROM PROGRAMMING CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37480E8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) M37480E8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480E8–’ Area for ASCII codes of the name of the product ‘M37480E8–’ ROM (16K) ROM (16K) ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. ROM PROGRAMMING CONFIRMATION FORM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37480E8-’ ]= $0000 .BYTE ‘M37480E8-’ SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-91B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8-XXXFP. h 3. Comments ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37480E8T-XXXSP GZZ-SH09-92B<56A0> SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480E8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480E8T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37480E8T-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37480E8T–’ Area for ASCII codes of the name of the product ‘M37480E8T–’ ROM (16K) ROM (16K) ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37480E8T-’ ]= $0000 .BYTE ‘M37480E8T-’ SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-92B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8T-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8T-XXXFP. h 3. Comments ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481E8-XXXSP GZZ-SH09-89B<56A0> SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37481E8–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) M37481E8-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481E8–’ Area for ASCII codes of the name of the product ‘M37481E8–’ ROM (16K) ROM (16K) ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37481E8-’ ]= $0000 .BYTE ‘M37481E8-’ SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-89B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8-XXXFP. h 3. Comments ROM number

Date: Section head signature Supervisor signature Company name Note : Please fill in all items marked h . Customerh Issuance signatureDate issued Submitted byTEL Date: Supervisor MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. M37481E8T-XXXSP GZZ-SH09-90B<56A0> SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP MITSUBISHI ELECTRIC Microcomputer name : Checksum code for entire EPROM (hexadecimal notation) (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481E8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481E8T–’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 EPROM type (indicate the type used) Microcomputer name : M37481E8T-XXXFP 27256 27512 000016 000F16 001016 3FFF16 400016 7FFF16 EPROM address 000016 000F16 001016 BFFF16 C00016 FFFF16 EPROM address Area for ASCII codes of the name of the product ‘M37481E8T–’ Area for ASCII codes of the name of the product ‘M37481E8T–’ ROM (16K) ROM (16K) ROM number h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. ]= $8000 .BYTE ‘M37481E8T-’ ]= $0000 .BYTE ‘M37481E8T-’ SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP MITSUBISHI ELECTRIC GZZ-SH09-90B<56A0> Recommend to writing the following pseudo-command to the assembler source file : 27256 27512EPROM type The pseudo-command Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. h 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8T-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8T-XXXFP. h 3. Comments ROM number

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE 32P2W–A 32P4B

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. 42P4B 44P6N–A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM MARK SPECIFICATION FORM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 32P2W (32-PIN SOP) MARK SPECIFICATION FORM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Mitsubishi IC catalog name A. Standard Mitsubishi Mark Note1 : If the special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit ) and mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the special mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be sub- mitted. 44P6N (44-PIN QFP) MARK SPECIFICATION FORM q! 1 #3 @3 Mitsubishi lot number (6-digit) Mitsubishi IC catalog name 3 : The standard Mitsubishi font is used for all characters ex- cept for a logo. Special logo required Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). q! 1 #3 @3 Mitsubishi IC catalog name and Mitsubishi lot number Note4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required. Customer’s parts number Note : The fonts and size of characters are standard Mitsubishi type. B. Customer’s Parts Number + Mitsubishi Catalog Name q! 1 #3 @3 C. Special Mark Required Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 7 characters : Only 0 ~ 9, A ~ Z,+,–, ⁄ , (, ), &, © , • (period), and , (comma) are usable.

© 1997 MITSUBISHI ELECTRIC CORP. KI-9711 Printed in Japan (ROD) II New publication, effective Nov. 1997. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

Rev. Rev. No. date

1.0 First Edition 971130

REVISION DESCRIPTION LIST 7480/7481 GROUP DATA SHEET (1/1) Revision Description