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IDT74SSTU32865 RENESAS | Alldatasheet

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COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY APRIL 2005 2005 Integrated Device Technology, Inc. DSC-6493/14c IDT74SSTU3286528-BIT 1:2 REGISTERED BUFFER WITH PARITY DESCRIPTION: The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32865 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V REF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32865 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PYTERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hard-wired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs. The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PYTERR pin (active low). APPLICATIONS:

• Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs
• Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D FEATURES:
• 1.8V Operation
• SSTL_18 style clock and data inputs
• Differential CLK input
• Control inputs compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
• Available in 160-pin CTBGA package COMMERCIAL TEMPERATURE RANGE

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FUNCTIONAL BLOCK DIAGRAM (1:2) PYTERR R D Q Q21A Q21B Q0A Q0B RESET CLK CLK DODT0, DODT1 R D Q R D Q (CS ACTIVE) VREF PARITY GENERATOR AND CHECKER QCS0A QCS0B R D Q QCS1A QCS1B R D Q QODT0A, QODT1A QODT0B, QODT1B QCKE0A, QCKE1A QCKE0B, QCKE1BR D Q R D Q PARIN D21 DCKE0, DCKE1 DCS1 CSGateEN DCS0 2 2 2 2

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY PIN CONFIGURATION A B C D E F NC PARIN NC QCKE1A Q18A Q17B Q19B Q21A Q21B NCVREF D9 GND VDDR VDDR Q1B Q1A D2 NC NC QCKE1B Q18B QODT0B Q19A NCD1 VDDR QCKE0A QCKE0B D11 D8 V DDL GND V DDL Q16B Q16A VDDL D5 V DDL GND NC NC GND GND QODT1B Q20B QODT1A Q20A GND GND Q17A QODT0A 12 3456789 10 11 12 G H J K L M D12 GND Q2B GND VDDR GND VDDLD18 CLK CLK D10 GND GND Q10B Q10A D15 GND Q5B VDDR VDDLCSGate EN RESET GNDD0 D14 GND GND Q6B Q6A GND DCS0 DCS1 GND VDDL GND VDDL VDDR GND VDDR GND QCS0B QCS1B QCS0A QCS1A VDDR VDDR Q2A Q5A N P R T U V D16 V DDL Q9BVDDRVDDLD17 D13 MCL MCL MCH Q3A Q7A Q13A Q0A Q8A D21 Q11B VDDR D19 DCKE0 Q4AVREF DCKE1 MCL PYTERR MCH Q3B NC D20 GND V DDL VDDL GND GND GND Q15B Q14B Q15A Q14A Q9A Q11A Q12A Q7B Q13B Q0B Q8BQ4BQ12B DODT1 DODT0 GND V DDL VDDL VDDR VDDR GND 160-BALL CTBGA TOP VIEW MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY

160 BALL CTBGA PACKAGE ATTRIBUTES

N P R T U V G H J K L M A B C D E F 12345678 9 1 0 1 1 1 2Top Mark N P R T U V G H J K L M A B C D E F 123456789101112 TOP VIEW BOTTOM VIEW SIDE VIEW

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs Outputs CSGate Dn, DODTn, RESET DCS0 DCS1 Enable CLK CLK DCKEn Qn Q CS QODT, QCKE HLL X ↑↓ LLL L HLL X ↑↓ HH L H H L L X L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HLH X ↑↓ LLL L HLH X ↑↓ HH L H H L H X L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HH L X ↑↓ LL H L HH L X ↑↓ HHH H H H L X L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HHH L ↑↓ LL H L HHH L ↑↓ HHH H H H H L L or H L or H X Q 0 (2) Q0 (2) Q0 (2) HHH H ↑↓ LQ 0 (2) HL HHH H ↑↓ HQ 0 (2) HH H H H H L or H L or H X Q 0 (2) Q0 (2) Q0 (2) L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L L L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. Output level before the indicated steady-state conditions were established.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY PARITY AND STANDBY FUNCTION TABLE(1) Inputs Output RESET DCS0 DCS1 CLK CLK ΣΣΣΣΣ of Inputs = H (D0 - D21) PARIN (2) PYTERR(3) HLH ↑↓ Even L H HLH ↑↓ Odd L L HLH ↑↓ Even H L HLH ↑↓ Odd H H HH L ↑↓ Even L H HH L ↑↓ Odd L L HH L ↑↓ Even H L HH L ↑↓ Odd H H HHH ↑↓ XX PYTERR0 (4) H X X L or H L or H X X PYTERR0 (4) L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating H NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. PARIN arrives one clock cycle after the data to which it applies 3. This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles, or until RESET is driven LOW. 4. Output level before the indicated steady-state conditions were established.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY REGISTER TIMING CLK CLK Dn PARIN Qn PTYERR tPDM, tPDMSS n - 1 n n +1 n + 2 n + 3 n + 4 n + 5 tSU tH tSU tH tPDM tPDH PYTERR PARIN Dn D Q DD D CLOCK LATCHING AND RESET FUNCTION (1) QnA QnB 22 22 PARITY LOGIC DIAGRAM NOTE: 1. This function holds the error for two cycles. See REGISTER TIMING diagram.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max. Unit VDD Supply Voltage Range –0.5 to 2.5 V VI(2,3) Input Voltage Range –0.5 to 2.5 V VO(2,3) Output Voltage Range –0.5 to VDD +0.5 V IIK Input Clamp Current V I < 0 ±50 mA VI > VDD IOK Output Clamp Current V O < 0 ±50 mA VO > VDD IO Continuous Output Current, ±50 mA VO = 0 to VDD VDD Continuous Current through each ±100 mA VDD or GND TSTG Storage Temperature Range –65 to +150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V ± 0.1V Symbol Parameter Min. Max. Unit fCLOCK Clock Frequency — 270 MHz tw Pulse Duration, CLK, CLK HIGH or LOW 1 — ns tACT(1,2) Differential Inputs Active Time — 10 ns tINACT(1,3) Differential Inputs Inactive Time — 15 ns tSU Setup Time DCSn before CLK↑, CLK↓ 0.7 — ns Data, PARIN, DODT, and DCKE before CLK↑, CLK↓ 0.5 — tH Hold Time Data, DCSn, PARIN, DCKE, and DODT 0.5 — ns after CLK↑, CLK↓ NOTES: 1. This parameter is not production tested. 2. Data and V REF inputs must be low a minimum time of t ACT max, after RESET is taken HIGH. 3. Data, V REF, and clock inputs must be held at valid levels (not floating) a minimum time of t INACT max, after RESET is taken LOW.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY TERMINAL FUNCTIONS Signal Terminal Group Name Type Description Ungated Inputs DCKE0, DCKE1 SSTL_18 DRAM function pins not associated with Chip Select DODT0, DODT1 Chip Select D0:D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW Gated Inputs Chip Select Inputs DCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN HIGH) when at least one Chip Select input is LOW. Re-Driven Outputs Q0A:Q21A SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge Q0B:Q21B of the clock QCS0-1A, B QCKE0-1A, B QODT0-1A, B Parity Input PARIN SSTL_18 Input parity is received on pin PARIN, and should maintain odd parity across the D0:D21 inputs, at the rising edge of the clock Parity Error Output PTYERR Open Drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Program Inputs CSGateEN 1.8V LVCMOS Chip Select Gate Enable. When HIGH, the D0:D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0:D21 inputs will be latched and redriven on every rising edge of the clock. Clock Inputs CLK, CLK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Miscellaneous MCL, MCH Must be connected to a Logic LOW or HIGH. Inputs RESET 1.8V LVCMOS Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. VREF 0.9V nominal Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Symbol Parameter Test Conditions Min. Typ. Max. Unit VOH VDD = 1.7V to 1.9V, IOH = – 6 mA 1.2 — — V VOL VDD = 1.7V to 1.9V, IOL = 6 mA — — 0.5 V II All Inputs V I = VDD or GND — — ±5 μA IDD Static Standby I O = 0, V DD = 1.9V, RESET = GND — — 200 μA Static Operating I O = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) —— 4 0 m A IDDD Dynamic Operating I O = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),— — — μA/Clock (Clock Only) CLK and CLK Switching 50% Duty Cycle. MHz IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode — — — Dynamic Operating V I = VIH (AC) or VIL (AC), CLK and CLK Switching at μA/Clock (Per Each Data Input) 50% Duty Cycle. One Data Input Switching at 1:2 Mode — — — MHz/Data Half Clock Frequency, 50% Duty Cycle. Input Dn V I = VREF ± 250mV, VDD = 1.8V 2.5 — 3.5 CI DCSn and CSGateENable 4 — 6 pF CLK and CLK VICR = 0.9V, VID = 600mV, VDD = 1.8V 4 — 6 RESET VI = VDD or GND, VDD = 1.8V 2 — 6 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V OPERATING CHARACTERISTICS, TA = 25ºC (1,2) Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 1.7 — 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V VTT Termination Voltage V REF– 40mV V REF VREF+ 40mV V VI Input Voltage 0 — V DD V VIH AC High-Level Input Voltage Data Inputs V REF+ 250mV — — V VIL AC Low-Level Input Voltage Data Inputs — — V REF– 250mV V VIH DC High-Level Input Voltage Data Inputs V REF+ 125mV — — V VIL DC Low-Level Input Voltage Data Inputs — — V REF– 125mV V VIH High-Level Input Voltage RESET, Cx 0.65 * VDD —— V VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V VID Differential Input Voltage CLK, CLK 600 — — mV IOH High-Level Output Current — — – 8 mA IOL Low-Level Output Current — — 8 mA TA Operating Free-Air Temperature 0 — 70 °C NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW.

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V ± 0.1V Symbol Parameter Min Max. Unit fMAX 270 — M H z tPDM(2) CLK and CLK to Q 1.41 2.15 ns tLH LOW to HIGH Delay, CLK and CLK to PYTERR 1.2 3 ns tHL HIGH to LOW Delay, CLK and CLK to PYTERR 13 n s tPLH LOW to HIGH Propagation Delay, RESET to PYTERR —3 n s tPDMSS(2,3) CLK and CLK to Q (simultaneous switching) — 2.35 ns tRPHL RESET to Q — 3 ns dV/dt_r Output slew rate from 20% to 80% 1 4 V/ns dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns dV/dt_Δ(4) Output slew rate from 20% to 80% — 1 V/ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY CL = 30 pF RL = 1KΩ DUT Out RL = 100Ω CLK Inputs TL = 50Ω TL = 350ps, 50Ω Test Point VDD VDD/2 LVCMOS RESET Input IDD VDD/2 tINACT tACT 10% 90% CLK VICR VID tPLH tPHL Output VOH VOL VICR VTT VTT VOH VOL VIH VIL tRPHL VDD/2 VTT LVCMOS RESET Input Output VICR VIDVICRInput tW VREF VIH VIL VREFInput VICR VID tSU tH CLK CLK VDD RL = 1KΩ Test Point Test Point CLK CLK CLK TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) Voltage Waveforms - Pulse Duration NOTES: 1. C L includes probe and jig capacitance. 2. I DD tested with clock and data inputs held at V DD or GND, and I O = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z O = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. V TT = V REF = V DD/2 6. V IH = V REF + 250mV (AC voltage levels) for differential inputs. V IH = V DD for LVCMOS input. 7. V IL = V REF - 250mV (AC voltage levels) for differential inputs. V IL = GND for LVCMOS input. 8. V ID = 600mV. 9. t PLH and t PHL are the same as t PDM. Load Circuit Voltage Waveforms - Setup and Hold Times Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Propagation Delay Times Voltage and Current Waveforms Inputs Active and Inactive Times

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY CL = 10 pF RL = 50ΩDUT Out Test Point VDD VOH 80% 20% VOL Output dv_f dt_f CL = 10 pF RL = 50Ω DUT Out Test Point VOL 20% 80% VOH Output dv_r dt_r TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) NOTES: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z O = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). Load Circuit: High-to-Low Slew-Rate Voltage Waveforms: High-to-Low Slew-Rate Load Circuit: Low-to-High Slew-Rate Voltage Waveforms: Low-to-High Slew-Rate

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY CL = 10 pF RL = 1KΩDUT Out Test Point VDD VOH VDD Output Waveform 2 LVCMOS RESET Input tPLH VDD/2 0.15V 0V VOH Output Waveform 2 0.15V 0V VDD VICR tHL Timing Inputs VICR VI(PP) Output Waveform 1 VDD/2 VOL VICR tHL Timing Inputs VICR VI(PP) TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) NOTES: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z O = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). Load Circuit: High-to-Low Slew-Rate Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to RESET RESET RESET RESET RESET Input) Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with Respect to Clock Inputs) Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to Clock Inputs)

COMMERCIAL TEMPERATURE RANGE IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY

ORDERING INFORMATION

PackageDevice TypeTemp. Range BKG Thin Profile, Fine Pitch, Ball Grid Array - Green 28-Bit 1:2 Registered Buffer with Parity 0°C to +70°C SSTU32 865

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