74670

54LS670 NSC | Alldatasheet

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Semiconductor ° TRI-STATE® 4-by-4 Register Files General Description These register files are organized as 4 words of 4 bits each, —_ and the read time (24 ns typical). The register file has a non- and separate on-chip decoding is provided for addressing _ volatile readout in that data is not lost when addressed. the four word locations to either write-in or retrieve data. ll inputs (except read enable and write enable) are butt- This permits writing into one location, and reading from an- ered to lower the drive requirements to one normal Series other word location, simultaneously. S4LS/74LS load, and input clamping diodes minimize Four data inputs are available to supply the word to be _switching transients to simplify system design. High speed, stored. Location of the word is determined by the write se- double ended AND-OR-INVERT gates are employed for the lect inputs A and B, in conjunction with a write-enable sig- read-address function and have high sink current, TRI- nal. Data applied at the inputs should be in its true form. | STATE outputs. Up to 128 of these outputs may be wire- That is, if a high level signal is desired from the output, a © AND connected for increasing the capacity up to 512 words. high level is applied at the data input for that particular bit | Any number of these registers may be paralleled to provide location. The latch inputs are arranged so that new data will —_n-bit word length. be accepted only if both internal address gate inputs are high. When this condition exists, data at the Dinputistrans- Features ferred to the latch output. When the write-enable input, Gw. Alternate Military/Aerospace device (54LS670) is avail- is high, the data inputs are inhibited and their levels can able. Contact a National Semiconductor Sales Office/ cause no change in the information stored in the internal Distributor for specifications. latches. When the read-enable input, Gp, is high, the data 8 For use as: outputs are inhibited and go into the high impedance state. ‘Soratch pad memory The individual address lines permit direct acquisition of data Buffer storage between processors stored in any four of the latches. Four individual decoding Bit storage in fast multiplication designs gates are used to complete the address for reading a word. Separate read/write addressing permits simultaneous When the read address is made in conjunction with the reading and writing read-enable signal, the word appears at the four outputs. Organized as 4 words of 4 bits This arrangement—data entry addressing separate from Expandable to 512 words of n-bits data read addressing and individual sense line — eliminates TRISTATE versions of DM54LS$170/DM74LS170 recovery times, permits simultaneous reading and writing, 5) access times 20 ni and is limited in speed only by the write time (27 ns typical) ‘ast access times 20 ns typ Connection Diagram Function Tables Duat-in-Line Package WRITE TABLE (SEE NOTES A, B, AND C) ATA we SELECT. UBLE OUTPUTS [_Writeinputs [Word vec "Bt Wa We Ow on “Os @2 [We Wa Gwi o 1 2s | w [is |i fis fro for fro fo LoL tL la@=D & Q A L H L Qo Q=D Qo Qo HL LI] Q Q Q=D @ HH L | Q Qo Q Q=D xX xX 4H Qo Qo Qo Qo READ TABLE (SEE NOTES A AND D) Readinputs [Outputs ao a oo ann CES CR CR CR CR Gln tL. Lt | WoBt woB2 woB3 WOB4 L H L W1iB1 =W1B2 W1B3) W1B4 ©: 3 eno zee eae H LL | w2B1 w2B2 W283 W2B4 DATA READ ourruTs H H L W3B1 W3B2 W3B3 W3B4 meurs SELECT xX xX _H z F4 4 Zz TUF /6436—1 Order Number 54LS670DMQB, 54LS670FMGB, Mote A onan Level. L = Low Level, X = Don't Gare, Z = High 54LS670LMQB, DMS4LS670J, DMS4LS670W, Now Bre oO ‘the four internal tip-top outputs wi assume : (Q = D) = The four selected output as pace ou rth the states applied to the four external data inputs. SGA, MIGA. NIGA or WIGA Note C: Qo = The level of Q before the indicated input conditions were Note D: WOB1 = The first bit of word 0, etc. 2-501

i g Absolute Maximum Ratings (note) \\f Military/Aerospace specified devices are required, Note: The “Absolute Maximum Ratings” are those values please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran- Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The Supply Voltage " parametric values defined in the “Electrical Characteristics” Input Voltage 7 table are not guaranteed at the absolute maximum ratings. Operating Free Air Temperature Range The “Recommended Operating Conditions” table will define DMS4LS and 54LS ~55°C to +125°C the conditions for actual device operation. DM74LS OC to +70°C Storage Temperature Range —65°C to + 150°C Recommended Operating Conditions * | een | a nom T Vis High Lovelinputvorage | 2 [Te Pv Vi LowLevelinputvorage | Tor TT oe TV low High LevelOutputcurent [| Ta PT =26 [ma lou towLevelutputcurent | | Te Tee [ms tw Write Enable Pulse Width ns (Note 3) isu seupting [oa | to ff fo fT Mews189 [wows | is ff fos [oT | tLATCH Latch Time for New Data 25 ns (Notes 2 & 3) " Temperate L-=| fee] |» | c Temperature Note 1: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the Previous address. If protection of data in the Drevious address, tsetup (Wa, Wa) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tly (Wa, Wa) wit! result in data being written into that location. Depending on the duration of the input conditions, one or a number of Previous addresses may have been written into. Note 2: Latch time is the time allowed for the intemal output of the latch to assume the state of new data. This is important only when attempting to read from a Jocation immediately after that location has received new data. Note 3: Ta = 25°C and Voc = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Symbol [rama | Gonaitions | me | (Note 1) units vi Input Clamp Voltage Voc = Min, ly = —18 mA re ee oe Vou High Level Output Voltage Voc = Min, lon = Max v Vit = Max, Vin = Min Vor | LowLevelOuputVotiage | Yoo =Minion=max | owes | [ozs | 04 | ee ec Ia High Levelinput Current | Voc = Max [orow | [| 2 | 2-502

Electrical Characteristics g ‘over recommended operating free air temperature (unless otherwise noted) (Continued) ° Symbol [paneer | conatons |e Now 1) [| baad h LowLevelinputCurent | Voc=Max | oRow | | | -o4 | weow [ow | TT 08] oma a loz Off-State Output Current Voc = Max, Vo = 2.7V with High Level Output Vin = Min, Vi. = Max BA Voltage Applied loz. Off-State Output Current Voc = Max, Vo = 0.4V with Low Level Output Vin = Min, Vi, = Max pA Voltage Applied Output Curent Woz) [owe | -2o | | 100 | loc Supply Curent Voo = Max Note 3) a Switching Characteristics at voc = 5v and Ta = 25°C (See Section 1 for Test Waveforms and Output Load) tPLH Propagation Delay Time Read Select 40 ns Low to High Level Output toQ {PHL Propagation Delay Time Read Select ns High to Low Level Output toQ tpLH Propagation Delay Time Write Enable ns Low to High Level Output toQ trae Propagation Delay Time Write Enable ns High to Low Level Output toQ tPLH Propagation Delay Time Data ns Low to High Level Output toa teHL. Propagation Delay Time Data ns High to Low Level Output toQ tezH Output Enable Time Read Enable ns to High Level Output to AnyQ tezi Output Enable Time Read Enable hs to Low Level Output to Any Q tPHZ Output Disable Time from Read Enable ns High Level Output (Note 4) to AnyQ teiz Output Disable Time from Read Enable ns Low Level Output (Note 4) to AnyQ Note 1: All typicals are at Voc = 5V, Ta = 25°C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: loc is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are open. Note 4: C. = 5 pF. 2-503

3 Logic Diagram

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