745181

74181 ETC | Alldatasheet

Document overview

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Technical content

FEATURES

• Provides 16 arithmetic operations: ADO, SUBTRACT, COMPARE, DOUBLE, plus 12 other arithmetic operations
• Provides all 16 logic operations of two variables: Exclusive·OR, Compare, AND, NAND, NOR, OR, plus 10 other logic operatlons
• Full lookahead carry for high­ speed arithmetic operation on long words

DESCRIPTION

The '181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the tour Function Select inputs (So - S3) and the Mode Control lnput (M), it can perform all the 16 possible logic operations or 16 different arithme­ tic operations on active HIGH or active LOW operands. The Function Table lists these operations. PIN CONFIGURATION December 4, 1985 74181, LS181, 5181 Arithmetic Logic Units 4-Blt Arithmetlc Loglc Unit Product Speciflcation TYPE TYPICAL PROPAGATION TYPICAL SUPPL Y CURRENT DELAY (TOTAL) 74181 22ns 91mA 74LS181 22ns 21mA 745181 11ns 120mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = sv ±5%; TA= o•c to +70°c Plastic DIP N74181N, N74LS181N, N74S181N NOTE: For information regarding devices processed to Military Specifications, see the Signetics Military Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 745 74LS Mode lnput 1ul 1Sul 1LSul A or B lnputs 3ul 3Sul 3LSul s lnputs 4ul 4Sul 4LSul Carry lnput Sui 5Sul 5LSul Fo - F3, = B, Cn + 4 Outputs 10ul 10Sul 10LSul G Output 10ul 10Sul 40LSul p Output 10ul 10Sul 20LSul NOTE: Where a 74 unit load (ul) is understood to be 40µA liH and -1.6mA 11L, a 745 unit load (Sui) is 50µA liH and -2.0mA l1L. and 74LS unit load (LSul) is 20µA l1H and -0.4mA liL· LOGIC SYMBOL 2 1 .. „ c,, M Vcc ""Pin 24 GNO =Pin 12 2322 21 20

• 1 a, A282 ,, " 10 11 5-350 LOGIC SYMBOL (IEEE/IEC) 17 19 18 11 , . A3 83 Cn+4 11 ... 14 G 17 853-0540 81502

When the Mode Control input (M) is HIGH, all interna! carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control lnput is LOW, the carńes are enabled and the device performs arithmetic operations on the two 4- bit words. The device incorporates full inter­ na! carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between pack­ ages using the signals P (Carry Propagate) and G (Carry Generale). P and G are not affected by carry in. When speed require­ ments are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn + 4) signal to the Carry input (Cn) of the next unit. For high-speed opera­ tion the device is used in conjunction with the LOGIC DIAGRAM Cn M Ao (7) (8) (2) l Fo Vrx; - Pin 24 GNO •Pin 12 () •Pin Numbers December 4, 1985 io (1) t.. ;;, ;;, '182 carry lookahead circuit. One carry looka­ head package is required for each group of tour ' 181 devices. Carry lookahead can be provided at various levels and offers high­ speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all tour F outputs are HIGH and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. The A = B output is open collector and can be wired-AND with other A = B outputs to give a compańson for mora than 4 bits. The A = B signal can also be used with the Cn + 4 signal to indicate A > B and A < B. The Function Table lists the arithmetic opera­ tions thai are performed without a carry in. An is, (23) (22) ę,., t Asi F2 5-351 Product Specification 74181, LS181, 5181 incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1 s complement), a carry out means borrow; thus, a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations thai are performed to the operands labeled inside the logic symbol. (18) i.. (15) (11) F3 p Cn+4 1os1 12s3 IH5 4H3J (17) ii I

Signetics Legie Products Product Specification Arithmetic Legie Units 74181, LS181, 5181 MODE SELECT- FUNCTION TABLE MODE SELECT INPUTS ACTIVE HIGH INPUTS & OUTPUTS S3 S2 S1 So Loglc Arlthmetlc (M=H) (M=L) (Cn=H) L L L L A A L L L H A+B A+B L L H L AB A+B L L H H Logical O minus 1 L H L L AB A plus AB L H L H B (A + B) plus AB L H H L AeB A minus B minus 1 L H H H AB AB minus 1 H L L L A+B A plus AB H L L H AeB A plus B H L H L B (A + B) plus AB H L H H AB AB minus 1 H H L L Logical 1 A plus A' H H L H A+B (A+ B) plus A H H H L A+B (A+ B) plus A H H H H A A minus 1 MODE SELECT INPUTS ACTIVE LOW INPUTS & OUTPUTS $3 S2 S1 So Loglc Arlthmetlc (M=H) (M=L) (Cn=L) L L L L A A minus 1 L L L H AB AB minus 1 L L H L A+B AB minus 1 L L H H Logical 1 minus 1 L H L L A+13 A plus (A+ B) L H L H Ei AB plus (A + B) L H H L A.B A minus B minus 1 L H H H A+B A+B H L L L AB A plus (A+ B) H L L H A.B A plus B H L H L B AB (A+ B) H L H H A+B A+B H H L L Logical o A plus A' H H L H AB AB plus A H H H L AB AB plus A H H H H A A L -LOW voltage H • HIGH voltage level

• Each bit is shifted to the next more significant position.
• • Arithmetic operations expressed in 2s complement notation. 2 1 23 22 21 20 19 18 2 1 2322 21 20 1918 AoBo ... , 81 A2 82 A3 83 Cn Cn+4 16 A=I 14 M ... 14 " „ G 15 15 10 11 13 10 13 Actlve High Operands Actlve Low Operands December 4, 1985 5-352

Signetics Legie Products Product Specification Arithmetic Logic Units 74181, LS181, 5181 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperatura range unless otherwise noted.) PARAM ETER 74 74LS 74S UNIT Vcc Supply voltage 7.0 7.0 7.0 V i1N I nput current -30 to +5 -30 to +1 -30 to +5 mA VouT Voltage applied to output in HIGH output state -0.5 to +Vcc -0.5 to +Vcc -0.5 to +Vcc V TA Operating free-air temperatura range o to 70 ·c RECOMMENDED OPERATING CONDITIONS 74 74LS 74S PARAM ETER UNIT Mln Nom Max Mln Nom Max Mln Nom Max V1H HIGH-level input voltage 2.0 2.0 2.0 V V1L LOW-level input voltage +0.8 +0.8 +0.8 V l1K I nput clamp current -12 -18 -18 mA ioH HIGH-level output current -800 -400 -1000 µA loL LOW-level output current 16 8 20 mA TA Operating free-air temperatura o 70 o 70 o 70 ·c I SUM MODE TEST TABLE I FUNCTION INPUTS: S0 = 53 = 4.5V, S 1 = s2 = M = ov OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER PARAMETER INPUT UNOER TEST TEST Apply 4.5V Apply GNO Apply 4.5V Apply GNO tPLH A; B; N one Remaining Cn F; tPHL A and B tPLH B; A; N one Remaining Cn F; tPHL A and B tPLH A1 B; N one N one Remaining p tPHL A and B, Cn tPLH B; A; N one N one Remaining p tPHL A and B, Cn tPLH A; N one B; Remaining Remaining G tPHL 8 A, Cn tPLH B; N one A; Remaining Remaining A, G tPHL 8 Cn tPLH A; N one B; Remaining Ramaining Cn+4 tPHL 8 A, Cn tPLH B; Nona A; Remaining Remaining Cn+4 tPHL 8 A, Cn tPLH Cn N one Nona All All Any F tPHL A 8 or Cn + 4 Dacember 4, 1985 5-353

Signetics Logic Products Product Specification Arithmetic Logic Units 74181, LS181, 5181 DIFF MODE TEST TABLE li FUNCTION INPUTS: 50 = 53 = 4.5V, 5 1 = s2 = M = ov OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER PARAM ETER INPUT UNDER TEST Apply 4.SV Apply GND Apply 4.SV Apply GND TEST lpLH A; N one 8; Remaining Remaining F; lpHL A 8, Cn lPLH 8; A; N one Remaining Remaining F; lpHL A 8, Cn IPLH A; N one 8; N one Remaining p IPHL A and 8, Cn lPLH 8; A; N one N one Remaining p lpHL A and 8, Cn IPLH A; 8; N one N one Remaining G IPHL A and 8, Cn lpLH 8; N one A; N one Remaining G IPHL A and Ei, Cn IPLH A; N one 8; Remaining Remaining A=B IPHL A 8, Cn IPLH 8; A; N one Remaining Remaining A=B IPHL A 8, Cn lpLH A; 8; N one N one Remaining Cn+4 lpHL A and 8, Cn IPLH 8; N one A; N one Remaining Cn+4 IPHL A and 8, Cn lpLH Cn N one N one All N one Any F lpHL A and 8 or Cn + 4 LOGIC MODE TEST TABLE Ili INPUT UNDER OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT FUNCTION PARAMETER TEST UNDER INPUTS Apply 4.SV Apply GND Apply 4.SV Apply GND TEST IPLH A; B; N one N one Remaining F; 51 = 52 = M = 4.5V lpHL A and 8, Cn 5o=53=0V IPLH 8; A; N one N one Remaining F; 51 = 52 = M = 4.5V lpHL A and 8, Cn 5o=53=0V December 4, 1985 5-354

Signetics Legie Products Product Specification Arithmetic Logic Units 74181, LS181, 5181 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperatura range unless otherwise noted.) 74181 74LS181 745181 PARAMETER TEST CONDITIONS 1 UNIT Mln Typ2 Max Min Typ2 Max Min Typ2 Max Vcc= MIN, loH =MAX Vcc= MIN, lol =4mA 0.25 0.4 V LOW-level Vol output voltage V1H =MIN, iQl=16mA 0.47 0.7 V V1l =MAX G output !Ql = BmA 0.35 0.5 V P output V1K lnput clamp Vcc= MIN, 11 = l1K -1.5 -1.5 -1.2 V voltage Mode input 1.0 0.1 1.0 mA lnput current at A or B inputs 1.0 0.3 1.0 mA 11 maximum input Vcc =MAX S inputs 1.0 0.4 1.0 mA voltage Carry input 1.0 0.5 1.0 mA Mode input 40 µA A or B 120 µA V1=2.4V inputs S inputs 160 µA HIGH-level input Carry input 200 µA l1H current Vcc= MAX Mode input 20 50 µA A or B 60 150 µA V1 =2.7V inputs S inputs BO 200 µA Carry input 100 250 µA Mode input -1.6 -0.4 mA A or B -4.B -1.2 mA V1=0.4V inputs S inputs -6.4 -1.6 mA LOW-level input Carry input -B -2 mA l1l current Vcc =MAX Mode input -2 mA A or B -6 mA V1=0.5V inputs S inputs -B mA Carry input -10 mA loH HIGH-level output V1H = MIN, V1l = MAX, VoH = 5.5V 250 100 250 µA current A=B only los Short-circuit Vcc =MAX Any output except -18 -57 -15 -100 -40 -100 mA output current3 A=B Supply current4 Note 4a BB 140 20 34 120 220 mA lee Vcc =MAX (total) Note 4b 94 150 21 37 120 220 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable typa. 2. All typical values are at Vcc = 5V, TA= 2s•c. 3. los is tested with Vour = + 0.5V and Vcc = Vcc MAX+ 0.5V. Not mare than one output should be shorted at a time and duration of the short circuit should not exceed one second. are at 4.5V, other inputs grounded, all outputs open. December 4, 1985 5-355 I

Signetics Logic Products Product Specification Arithmetic Logic Units 74181, LS181, 5181 AC ELECTRICAL CHARACTERISTICS TA= 25°C, Vcc = 5.ov 74 74LS 748 PARAMETER TEST CONDITIONS CL= 15pf CL= 15pf CL= 15pf UNIT RL=400Q RL=2kQ RL=2aon Mln Max Mln Max Mln Max tPLH Propagation delay M = OV, Sum or Diff Mode 18 27 10.5 tPHL Cn to Cn+4 see Waveform 2 and Tables I & li 19 20 10.5 ns tPLH Propagation delay M = OV, Sum or Diff Mode 19 26 12 tPHL Cn to F outputs see Waveform 2 and Tables I & li 18 20 12 ns tPLH Propagation delay M = S1 = S2 = OV, So = S3 = 4.5V 19 29 12 tPHL A or B inputs to G output Sum Mode, see Waveform 2 and 19 23 12 ns Table I tPLH Propagation delay M = So = S3 = OV, S1 = S2 = 4.5V 25 32 15 tPHL A or B inputs to G output Diff Mode, see Waveform 3 and 25 32 15 ns Table li tPLH Propagation delay M = S1 = S2 = OV, So = S3 = 4.5V 19 30 12 tPHL A or B inputs to j5 output Sum Mode, see Waveform 2 and 25 30 12 ns Table I tPLH Propagation delay M = So = S3 = OV, S1=S2=4.5V 25 30 15 tPHL A or B inputs to P output Diff Mode, see Waveform 3 and 25 33 15 ns Table li tPLH Propagation delay M = S1 = S2 = OV, So = S3 = 4.5V 42 32 16.5 tPHL A; or B; inputs to F; outputs Sum Mode, see Waveform 2 and 32 20 16.5 ns Table I tPLH Propagation delay M = So = S3 = OV, 81=S2=4.5V 48 32 20 tPHL A; or B; inputs to "F; outputs Diff Mode, see Waveform 3 and 34 32 22 ns Table li tPLH Propagation delay M = 4.5V, Logic Mode 48 33 20 tPHL A; or B; inputs to "F; outputs see Waveform 2 and Table Ili 34 38 22 ns tPLH Propagation delay M = OV, So = S3 = 4.5V, S1 = S2 = OV 43 38 18.5 tPHL A or B inputs to Cn + 4 Sum Mode, see Waveform 1 and 41 38 18.5 ns output Table I tPLH Propagation delay M = OV, So = S3 = OV, S1 = S2 = 4.5V 50 41 23 tPHL A or B inputs to Cn + 4 Diff Mode, see Waveform 4 and 50 41 23 ns outputs Table li tPLH Propagation delay M = So = S3 = OV, S1=S2=4.5V 50 50 23 tPHL A or B inputs to A=B Diff Mode, see Waveform 3 and 48 62 30 ns output Table li December 4, 1985 5-356

V1NJvM ~VM L,PHLj ~PL1 Vour ~VM F WF07570S VM • 1.5V for 74 and 74S; VM - 1.3V for 74LS Waveform 1 V.{~VM fvM I I Vi _j-vM ~VM L.-j '-'"'"! Vour ~VM F:. WAlOS20S VM = 1.5V for 74 and 745; VM"' 1.3V for 74LS Waveform 3 TEST CIRCUITS AND WAVEFORMS vcc RT vcc r -OPEN - ..., I COLLECTOR I RL I OUTPUT I A„a ONLY : 4:~c : o I I : I I Test Clrcult For 74 Totem-Pole Outputs DEFINITIONS Product Specification 74181, LS181, 5181 V1N~VM f.vM ~IPHLJ ~PLHI Vour ~VM F WF07580S VM • 1.5V for 74 and 748; VM • 1.3V for 74LS Waveform 2 v;. __jvM ~VM I I Vi~VM {vM Vour ~VM r:; WF08530S vM- 1.SV for 74 and 745; VM „ 1.3V tor 74LS Waveform 4 AMP(V) VM"" 1.3V tor 74LS; VM • 1 .SV for all other TIL familias. lnput Pulse Deflnltlon INPUT PULSE REQUIREMENTS AL = Load resistor to Vcc; see AC CHARACTERISTICS for value CL - Load capacitance includes jig and probe capacitance; FAMILY see AC CHARACTERISTICS for value. RT = T ermination resistance should be equal to Zour of Pulse Generators. D - Diodes are 1 N916, 1 N3064, or equivalent. trLH• trHL Values should be less than or equal to the table entries. December 4, 1985 Amplltude 74 3.0V 74LS 3.0V 74S 3.0V 5-357 Rep. Rate Pulae Wldth trLH trHL 1MHz 500ns 7ns 7ns 1MHz 500ns 15ns 6ns 1MHz soons 2.5ns 2.5ns li