7442

TDA7442 STMICROELECTRONICS | Alldatasheet

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Technical content

Table 2. Quick Reference Data Table 3. Thermal Data Table 4. Absolute Maximum Ratings Table 5. Electrical Characteristics 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.

1.4 Vp-p R in → Rout, Lin → Lout

Table 5. Electrical Characteristics (continued) 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.

0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.

3.1 Data Validity

and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

3.2 Start and Stop Conditions

stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

3.3 Byte Format

bit. The MSB is transferred first.

3.4 Acknowledge

The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. the master transmitter can generate the STOP information in order to abort the transfer.

3.5 Transmission without Acknowledge

it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 5. Data Validity on the I Figure 6. Timing Diagram of I2CBUS Figure 7. Acknowledge on the I2CBUS

4 SOFTWARE SPECIFICATION

The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7442D ■ A subaddress bytes ■ A sequence of data (N byte + acknowledge) ■ A stop condition (P) ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment

4.1 EXAMPLES

4.1.1 No Incremental Bus

The TDA7442D receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.

4.1.2 Incremental Bus

The TDA7442D receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (in- cremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBAD- DRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition. S 1 0 0 0 0 0 A 0 ACK ACK DATA ACK P MSB LSB MSB LSB MSB LSB CHIP ADDRESS D95AU226A B DATA SUBADDRESS DATA 1 to DATA n S 1 0 0 0 0 0 A 0 ACK ACK DATA ACK P MSB LSB MSB LSB MSB LSB CHIP ADDRESS D95AU306 0 D3 SUBADDRESS DATA X X X D2 D1 D0 S 1 0 0 0 0 0 A 0 ACK ACK DATA ACK P MSB LSB MSB LSB MSB LSB CHIP ADDRESS D95AU307 1 D3 SUBADDRESS DATA 1 to DATA n X X X D2 D1 D0

5 DATA BYTES

Address = 80(HEX)

5.1 Function Selection:

The first byte (subaddress) B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 Input Attenuation Selection INPUT ATTENUATION = 0 ~ -31.5dB MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 BXXX0000 I N P U T A T T E N U A T I O N B X X X 0 0 0 1 SURROUND & OUT & EFFECT CONTROL B X X X 0 0 1 0 PHASE RESISTOR BXXX0011 B A S S BXXX0100 T R E B L E B X X X 0 1 0 1 SPEAKER ATTENUATION "L" B X X X 0 1 1 0 SPEAKER ATTENUATION "R" BXXX0111 N O T A L L O W E D BXXX1000 N O T A L L O W E D B X X X 1 0 0 1 INPUT MULTIPLEXER MSB LSB INPUT ATTENUATION D7 D6 D5 D4 D3 D2 D1 D0 0.5 dB STEPS 10 0 0 0 10 0 1 - 0 . 5 10 1 0 - 1 10 1 1 - 1 . 5 11 0 0 - 2 11 0 1 - 2 . 5 11 1 0 - 3 11 1 1 - 3 . 5 4 dB STEPS 1000 0 1001 - 4 1010 - 8 1011 - 1 2 1100 - 1 6 1101 - 2 0 1110 - 2 4 1111 - 2 8

5.2 Surround Selection

D7 D6 D5 D4 D3 D2 D1 D0 SURROUND MODE 0 0 SIMULATED STEREO

01 M U S I C

10 O F F

MSB LSB SURROUND PHASE RESISTOR D7 D6 D5 D4 D3 D2 D1 D0 PHASE SHIFT 1 (K Ω) 00 1 2 01 1 4 10 1 8 11 3 7 BASS SELECTION MSB LSB BASS D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS X XX10000 - 1 4 X XX10001 - 1 2 X XX10010 - 1 0 X XX10011 - 8 X XX10100 - 6 X XX10101 - 4 X XX10110 - 2 X XX10111 0 X XX11111 0

D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS X XX11110 2 X XX11101 4 X XX11100 6 X XX11011 8 X XX11010 1 0 X XX11001 1 2 X XX11000 1 4 SPEAKER SELECTION MSB LSB SPEAKER/ATT D7 D6 D5 D4 D3 D2 D1 D0 1 dB STEPS X 000 0 X 001 - 1 X 010 - 2 X 011 - 3 X 100 - 4 X 101 - 5 X 110 - 6 X 111 - 7 8 dB STEPS X0000 0 X0001 - 8 X0010 - 1 6 X0011 - 2 4 X0100 - 3 2 X0101 - 4 0 X0110 - 4 8 X0111 - 5 6 X1000 - 6 4 X1001 - 7 2 MUTE X101X X11XX X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB TREBLE SELECTION MSB LSB TREBLE D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS 00001110 - 1 4 00011110 - 1 2 00101110 - 1 0 00111110 - 8 01001110 - 6 01011110 - 4

5.2 Surround Selection (continued)

X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ~ -79dB MSB LSB TREBLE D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS 01101110 - 2 01111110 0 11111110 0 11101110 2 11011110 4 11001110 6 10111110 8 10101110 1 0 10011110 1 2 10001110 1 4 INPUT SELECTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 INPUT MULTIPLEXER X 000 I N 2 X 010 I N 3 X 100 I N 4 X 110 I N 1 TREBLE SELECTION MSB LSB TREBLE D7 D6 D5 D4 D3 D2 D1 D0 2 dB STEPS 00001110 - 1 4 00011110 - 1 2 00101110 - 1 0 00111110 - 8 01001110 - 6 01011110 - 4 01101110 - 2 01111110 0 11111110 0 11101110 2 11011110 4 11001110 6 10111110 8 10101110 1 0 10011110 1 2 10001110 1 4 INPUT SELECTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 INPUT MULTIPLEXER X0 0 0 I N 2 X0 1 0 I N 3 X1 0 0 I N 4 X1 1 0 I N 1

Figure 15. PIN: BASS-LI, BASS-RI Figure 16. PIN: BASS-LO, BASS-RO

Figure 17. SO-28 Mechanical Data & Package Dimensions

Figure 18. SDIP-32 Mechanical Data & Package Dimensions

Table 7. Revision History

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States TDA7442 - TDA7442D