M74HC374 STMICROELECTRONICS | Alldatasheet
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■ HIGH SPEED: fMAX = 90MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: I CC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) ■ SYMMETRICAL OUTPUT IMPEDANCE: OH | = IOL = 6mA (MIN) ■ BALANCED PROPAGATION DELAYS: t PLH ≅ tPHL ■ WIDE OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V ■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
DESCRIPTION
The M74HC374 is an high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate C 2MOS technology. This 8 bit D-TYPE FLIP FLOP is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is high the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HC374B1R SOP M74HC374M1R M74HC374RM13TR TSSOP M74HC374TTR TSSOPDIP SOP
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE X: Don’t Care Z: High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays PIN No SYMBOL NAME AND FUNCTION 1O E 3 State Output Enable Input (Active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3 State Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs
11 CK Clock Input (LOW to
HIGH, edge triggered)
10 GND Ground (0V)
CC Positive Supply Voltage INPUTS OUTPUT OE CK D Q HXXZ L X NO CHANGE LL L LH H
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ICC or IGND DC V CC or Ground Current ± 70 mA PD Power Dissipation 500(*) mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature -55 to 125 °C tr, tf Input Rise and Fall Time V CC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns
(V) TA = 25°C -40 to 85°C -55 to 125°C VIH High Level Input Voltage 2.0 1.5 1.5 1.5 V4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Low Level Input Voltage 2.0 0.5 0.5 0.5 V4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 VOH High Level Output Voltage V VOL Low Level Output Voltage V II Input Leakage Current 6.0 VI = VCC or GND ± 0.1 ± 1 ± 1 µA IOZ High Impedance Output Leakage Current
6.0 VI = VIH or VIL
VO = VCC or GND ± 0.5 ± 5 ± 10 µA ICC Quiescent Supply Current 6.0 VI = VCC or GND 44 0 8 0 µA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC /8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 30 + 17 x n (pF) Symbol Parameter Test Condition Value UnitVCC (V) C L (pF) TA = 25°C -40 to 85°C -55 to 125°C tTLH tTHL Output Transition Time 2.0 25 60 75 90 ns4 . 5 7 1 21 51 8 6 . 0 6 1 01 31 5 tPLH tPHL Propagation Delay Time (CLOCK - Q) 2.0 45 140 175 210 ns4.5 15 28 35 42 6.0 13 24 30 36 2.0 150 60 190 240 285 ns4.5 20 38 48 57 6.0 17 32 41 48 t PZL tPZH High Impedance Output Enable Time 2.0
50 R L = 1 KΩ
ns4.5 13 27 34 41 6.0 11 23 29 35 2.0 150 R L = 1 KΩ 54 185 230 280 ns4.5 18 37 46 56 6.0 15 31 39 48 tPLZ tPHZ High Impedance Output Disable Time 2.0 50 R L = 1 KΩ 30 125 155 190 ns4.5 14 25 31 38 6.0 13 21 26 32 fMAX Maximum Clock Frequency 2.0 6.2 18 5 4.2 MHz4.5 31 75 25 21 6.0 37 90 30 25 tW(L) tW(H) Minimum Pulse Width (CLOCK) 2.0 15 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 6 1 31 61 9 ts Minimum Set-up Time 2.0 25 75 95 110 ns4 . 5 6 1 51 92 2 6 . 0 4 1 31 61 9 th Minimum Hold Time 2.0 000 ns4.5 0 0 0 6.0 0 0 0 Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C C IN Input Capacitance 5 1 01 01 0 p F C OUT Output Capacitance 10 pF C PD Power Dissipation Capacitance (note 47 pF
C L = 50pF/150pF or equivalent (includes jig and probe capacitance) R 1 = 1KΩ or equivalent R T = ZOUT of pulse generator (typically 50Ω ) WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, CK FMAX, Dn TO CK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) TEST SWITCH tPLH , tPHL Open tPZL , tPLZ VCC tPZH , tPHZ GND
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: MINIMUM PULSE WIDTH (CK) (f=1MHz; 50% duty cycle)
DIM. mm. inch a1 0.254 0.010 B 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L 3.3 0.130 Z 1.34 0.053 Plastic DIP-20 (0.25) MECHANICAL DATA P001J
DIM. mm. inch A 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M 0.75 0.029 S8 ° ( m a x . ) SO-20 MECHANICAL DATA PO13L
DIM. mm. inch A 1.2 0.047 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 e 0.65 BSC 0.0256 BSC K0 ° 8 °0 ° 8 ° TSSOP20 MECHANICAL DATA c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 0087225C
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