IDT29FCT52AT IDT | Alldatasheet
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Integrated Device Technology, Inc. FAST CMOS OCTAL REGISTERED TRANSCEIVERS IDT29FCT52AT/BT/CT/DT IDT29FCT2052AT/BT/CT IDT29FCT53AT/BT/CT The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES:
- Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – V OH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages
- Features for 29FCT52/29FCT53T: – A, B, C and D speed grades – High drive outputs (-15mA I OH , 64mA IOL ) – Power off disable outputs permit “live insertion”
- Features for 29FCT2052T: – A, B and C speed grades – Resistor outputs (-15mA I OH , 12mA IOL Com.) (-12mA IOH , 12mA IOL Mil.) – Reduced system switching noise DESCRIPTION: The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/ CT are 8-bit registered transceivers built using an advanced dual metal CMOS technology. Two 8-bit back-to-back regis- ters store data flowing in both directions between two bidirec- tional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA. The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/ CT are non-inverting options of the IDT29FCT53AT/BT/CT. The IDT29FCT2052AT/BT/CT has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The IDT29FCT2052T part is a plug-in replacement for IDT29FCT52T part. FUNCTIONAL BLOCK DIAGRAM (1) CPA A 0 2629 drw 01 CEA A 1 A 2 A 3 A 4 A 5 A 6 A 7 B 0 OEB B 1 B 2 B 3 B 4 B 5 B 6 B 7 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 CE CP A Reg. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 CE CP B Reg. OEA CPB CEB NOTE: 1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is the inverting option. MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1995 1995 Integrated Device Technology, Inc. 6.1 DSC-4224/5
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 2 PIN CONFIGURATIONS 12GND Vcc P24-1 D24-1 SO24-2 SO24-7* SO24-8* E24-1 A A 5 A 4 A 3 A 2 CEB CEA CPB CPA OEA A 1 A 0 A 7B 6 B 5 B 4 B 3 B 2 B 1 B B 7 OEB 2629 drw 02 L28-1 12 13 14 15 16 17 18 432 28 27 26 INDEX 2629 drw 03 B 3 B 2 B 1 B 0 A 5 A 4 A 3 A 2 A 1 A 0OEB NC NC GND CEB CEA CPB CPA OEA NC B 4 B 5 Vcc A 6 A 7 B 6 NC B 7 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW LCC TOP VIEW * For 29FCT52/29FCT2052AT/BT/CT only PIN DESCRIPTION Name I/O Description A0-7 I/O Eight bidirectional lines carrying the A Register inputs or B Register outputs. B0-7 I/O Eight bidirectional lines carrying the B Register inputs or A Register outputs. CPA I Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. CEA I Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions. OEB I Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When OEB is HIGH, the B0-7 outputs are in the high-impedance state. CPB I Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. CEB I Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions. OEA I Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When OEA is HIGH, the A0-7 outputs are in the high-impedance state. 2629 tbl 01
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 3 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change ↑ = LOW-to-HIGH Transition REGISTER FUNCTION TABLE (1) (Applies to A or B Register) Inputs Internal DC P CECE Q Function X X H NC Hold Data L ↑ L L Load Data H ↑ LH 2629 tbl 02 OUTPUT CONTROL (1) Internal Y-Outputs OEOE Q 52/2052 53 Function H X Z Z Disable Outputs L L L H Enable Outputs LHHL NOTE: 2629 tbl 03 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance CAPACITANCE (TA = +25°C, f = 1.0MHz)ABSOLUTE MAXIMUM RATINGS (1) 2529 lnk 04 Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. This parameter is measured at characterization but not tested. 2640 lnk 05 Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage with Respect to GND VTERM (3) Terminal Voltage with Respect to GND –0.5 to V CC +0.5 –0.5 to VCC +0.5 V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 0.5 0.5 W IOUT DC Output Current –60 to +120 –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V CC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 4 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V II H Input HIGH Current(4) VCC = Max. V I = 2.7V — — ±1 µA II L Input LOW Current(4) V I = 0.5V — — ±1 IOZH High Impedance Output Current VCC = Max. V O = 2.7V — — ±1 µA IOZL (3-State Output pins)(4) VO = 0.5V — — ±1 II Input HIGH Current (4) VCC = Max., VI = VCC (Max.) — — ±1 µA VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V VH Input Hysteresis — — 200 — mV ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA OUTPUT DRIVE CHARACTERISTICS FOR 29FCT52T/29FCT53T Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VOH Output HIGH Voltage V CC = Min. VIN = VIH or VIL IOH = –6mA MIL. IOH = –8mA COM'L. 2.4 3.3 — V IOH = –12mA MIL. IOH = –15mA COM'L. 2.0 3.0 — V VOL Output LOW Voltage V CC = Min. VIN = VIH or VIL IOL = 48mA MIL. IOL = 64mA COM'L. — 0.3 0.55 V IOS Short Circuit Current V CC = Max., VO = GND(3) –60 –120 –225 mA IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA OUTPUT DRIVE CHARACTERISTICS FOR 29FCT2052T Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit IODL Output LOW Current V CC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) 16 48 — mA IODH Output HIGH Current V CC = 5V, VIN = VIH or V IL,VOUT = 1.5V(3) –16 –48 — mA VOH Output HIGH Voltage V CC = Min. VIN = VIH or VIL IOH = –12mA MIL. IOH = –15mA COM'L. 2.4 3.3 — V VOL Output LOW Voltage V CC = Min. VIN = VIH or VIL IOL = 12mA — 0.3 0.50 V NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at T A = –55°C. 5. This parameter is guaranteed but not tested. 2629 tbl 06 2629 tbl 07 2629 tbl 08
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 5 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) — 0.5 2.0 mA ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open OE A or OEB = GND VIN = VCC VIN = GND FCTxxxT — 0.15 0.25 mA/ MHz One Input Toggling 50% Duty Cycle FCT2xxxT — 0.06 0.12 IC Total Power Supply Current(6) VCC = Max. Outputs Open VIN = VCC VIN = GND FCTxxxT — 1.5 3.5 mA fCP = 10MHz 50% Duty Cycle FCT2xxxT — 0.6 2.2 OEA or OEB = GND V IN = 3.4V FCTxxxT — 2.0 5.5 One Bit Toggling at fi = 5MHz 50% Duty Cycle V IN = GND FCT2xxxT 1.1 4.2 VCC = Max. Outputs Open VIN = VCC VIN = GND FCTxxxT — 3.8 7.3 (5) fCP = 10MHz 50% Duty Cycle FCT2xxxT — 1.5 4.0 (5) OEA or OEB = GND V IN = 3.4V FCTxxxT — 6.0 16.3 (5) Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle V IN = GND FCT2xxxT — 3.8 13.0 (5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DH N T + ICCD (fCP/2 + fiN i) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) D H = Duty Cycle for TTL Inputs High N T = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency N i = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 2629 tbl 09
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 6 SWITCHING CHARACTERISTICS OVER OPERATING RANGE 29FCT52AT/53AT 29FCT2052AT 29FCT52BT/53BT 29FCT2052BT Com'l. Mil. Com'l. Mil. tPLH tPHL Propagation Delay CPA, CPB to An, Bn C L = 50pF tPZH tPZL Output Enable Time tPHZ tPLZ Output Disable Time tSU Set-up Time, HIGH or LOW An, Bn to CPA, CPB 2.5 — 2.5 — 2.5 — 2.5 — ns tH Hold Time, HIGH or LOW An, Bn to CPA, CPB 2.0 — 2.0 — 1.5 — 1.5 — ns tSU Set-up Time, HIGH or LOW CEA, CEB to CPA, CPB 3.0 — 3.0 — 3.0 — 3.0 — ns tH Hold Time, HIGH or LOW CEA, CEB to CPA, CPB 2.0 — 2.0 — 2.0 — 2.0 — ns tW Clock Pulse Width HIGH or 2629 tbl 10 NOTES: 2629 tbl 11 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 29FCT52CT/53CT 29FCT2052CT 29FCT52DT Com'l. Mil. Com'l. Mil. tPLH tPHL Propagation Delay CPA, CPB to An, Bn C L = 50pF tPZH tPZL Output Enable Time tPHZ tPLZ Output Disable Time tSU Set-up Time, HIGH or LOW An, Bn to CPA, CPB 2.5 — 2.5 — 1.5 — — — ns tH Hold Time, HIGH or LOW An, Bn to CPA, CPB 1.5 — 1.5 — 1.0 — — — ns tSU Set-up Time, HIGH or LOW CEA, CEB to CPA, CPB 3.0 — 3.0 — 2.0 — — — ns tH Hold Time, HIGH or LOW CEA, CEB to CPA, CPB 2.0 — 2.0 — 1.0 — — — ns tW Clock Pulse Width HIGH or
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 7 TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS PROPAGATION DELAY SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH SWITCH POSITION Pulse Generator R T D.U.T. V CC VIN C L V OUT 50pF 500Ω 500Ω 7.0V 1.5V 1.5V 1.5V 1.5V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 1.5V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 1.5V tPLH tPHL tPHL VOL CONTROL INPUT 1.5V 3.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZtPZL tPZH tPHZ 3.5V 1.5V 1.5V ENABLE DISABLE VOH PRESET CLEAR CLOCK ENABLE ETC. Test Switch Disable Low Enable Low Closed All Other Tests Open Open Drain DEFINITIONS: C L= Load capacitance: includes jig and probe capacitance. R T = Termination resistance: should be equal to ZOUT of the Pulse Generator. 2629 lnk 12 2629 drw 03 2629 drw 04 2629 drw 05 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 2629 drw 07 2629 drw 06
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT FAST CMOS OCTAL REGISTERED TRANSCEIVERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.1 8
ORDERING INFORMATION
X Process Blank B Commercial MIL-STD-883, Class B P D E L SO PY Q Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package 52AT 53AT 52BT 53BT 52CT 53CT 52DT Non-inverting Octal Registered Transceiver Inverting Octal Registered Transceiver XX Device Type 2629 drw 08 X FamilyTemp. Range XX Blank B Blank High Drive Balanced Drive –55 °C to +125°C 0°C to +70°C