TDA7429L STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
n INPUT ATTENUATION CONTROL IN 0.5dB STEP n TREBLE MIDDLE AND BASS CONTROL n FOUR SPEAKERS ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION n SUBWOOFER OUTPUT (L+R) CONTROLLED IN 1dB STEP INPUTS n ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
DESCRIPTION
The TDA7429L is volume tone (bass middle and tre- ble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems, providing also an additional subwoofer control. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are ob- tained. SDIP42 ORDERING NUMBER: TDA7429L
3 BAND EQUALIZER AUDIO PROCESSOR
Figure 1. Test Circuit
Figure 2. Pin Connection Table 1. Quick Reference Data
Figure 3. Block Diagram.
Table 2. Thermal Data Table 3. Absolute Maximum Ratings Table 4. Electrical Characteristics (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
(G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified).
1.0 I2C BUS INTERFACE
1.1 Data Validity
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
1.2 Start and Stop Conditions
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
1.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
1.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). transmitter can generate the STOP information in order to abort the transfer.
1.5 Transmission without Acknowledge
waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 4. Data validity on the I2Cb u s Figure 5. Timing Diagram of I2C bus
Figure 6. Acknowledge on the I2C bus
2.0 SOFTWARE SPECIFICATION
2.1 Interface Protocol
3.0 EXAMPLES
3.1 No Incremental Bus
mental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
3.2 Incremental Bus
concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
Table 5. Function Selection Table 6. Input Attenuation Selection
Table 7. Out & (L+R) & Subwoofer Selection Table 8. Bass Selection
- SPAEAKER/AU XATTENUATI ON = 0dB to 79dB
Table 9. Speaker/Aux Att. R & L Selection
Table 10. Middle & Treble Selection
Table 11. Input/recout L & R Selection Table 12. Power on reset
SDIP42 (0.600”)A1 Be B1 D LA c E Gage Plane .015 0,38 E SDIP42 DIM. mm inch A 5.08 0.20 A1 0.51 0.020 E 15.24 16.00 0.60 0.629 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 OUTLINE AND MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com TDA7429L