74221

MM74HC221A FAIRCHILD | Alldatasheet

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Features

■ Typical propagation delay: 40 ns ■ Wide power supply range: 2V–6V ■ Low quiescent current: 80 µA maximum (74HC Series) ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads ■ Simple pulse width formula T = RC ■ Wide pulse range: 400 ns to ∞ (typ) ■ Part to part variation: ±5% (typ) ■ Schmitt Trigger A & B inputs enable infinite signal input rise or fall times Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP , SOIC, SOP and TSSOP Top View Timing Component Note: Pin 6 and Pin 14 must be hard-wired to GND. Order Number Package Number Package Description MM74HC221AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC221ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC221AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC221AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide

www.fairchildsemi.com 2 MM74HC221A Truth Table H = HIGH Level L = LOW Level ↑= Transition from LOW-to-HIGH ↓= Transition from HIGH-to-LOW /c12 = One HIGH Level Pulse /c13 = One LOW Level Pulse X = Irrelevant Logic Diagram Inputs Outputs Clear AB Q Q LX X LH XH X L H XX L L H HL ↑ /c12/c13 H ↓ H /c12/c13 ↑ LH /c12/c13

3 www.fairchildsemi.com MM74HC221A Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/ °C from 65°C to 85°C. Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH , and VOL ) occur for HC at 4.5V. Thus the 4.5V values should be used when rent (IIN, ICC , and IOZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC ) −0.5V to +7.0V DC Input Voltage (VIN) −1.5V to VCC +1.5V DC Output Voltage (VOUT ) −0.5V to VCC +0.5V Clamp Diode Current (IIK, IOK ) ±20 mA DC Output Current, per pin (IOUT ) ±25 mA DC V CC or GND Current, per pin (ICC ) ±50 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (T (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 6 V DC Input or Output Voltage (VIN, VOUT )0 V CC V Operating Temperature Range (TA) −40 +85 °C Maximum Input Rise and Fall Time (Clear Input) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum LOW Level 2.0V 0.3 0.3 0.3 V Input Voltage 4.5V 0.9 0.9 0.9 V 6.0V 1.2 1.2 1.2 V VOH Minimum HIGH Level V IN = VIH or VIL V IN = VIH or VIL VOL Maximum LOW Level V IN = VIH or VIL Output Voltage |I OUT | ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VIN = VIH or VIL IIN Maximum Input Current V IN = VCC or GND 6.0V ±0.5 ±5.0 ±5.0 µA (Pins 7, 15) IIN Maximum Input Current V IN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA (all other pins) ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 8.0 80 160 µA Current (standby) I OUT = 0 µA ICC Maximum Active Supply V IN = VCC or GND 2.0V 36 80 110 130 µA

www.fairchildsemi.com 4 MM74HC221A VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns C L = 50 pF, tr = tf = 6 ns (unless otherwise specified) Note 5: C PD determines the no load dynamic power consumption, PD = CPD VCC 2f + ICC VCC , and the no load dynamic current consumption, IS = CPD VCC f + ICC . Symbol Parameter Conditions Typ Guaranteed Units Limit tPLH Maximum Trigger Propagation 22 36 ns Delay A, B or Clear to Q tPHL Maximum Trigger Propagation 25 42 ns Delay A, B or Clear to Q tPHL Maximum Propagation Delay Clear to Q 20 31 ns tPLH Maximum Propagation Delay Clear to Q 22 33 ns tW Minimum Pulse Width A, B or Clear 14 26 ns tREM Minimum Clear Removal Time 0n s tWQ(MIN) Minimum Output Pulse Width C EXT = 28 pF 400 ns R EXT = 2 kΩ tWQ Output Pulse Width C EXT = 1000 pF 10 µs R EXT = 10 kΩ Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits tPLH Maximum Trigger Propagation 2.0V 77 169 194 210 ns Delay A, B or Clear to Q 4.5V 26 42 51 57 ns 6.0V 21 32 39 44 ns tPHL Maximum Trigger Propagation 2.0V 88 197 229 250 ns Delay A, B or Clear to Q 4.5V 29 48 60 67 ns 6.0V 24 38 46 51 ns tPHL Maximum Propagation 2.0V 54 114 132 143 ns Delay Clear to Q 4.5V 23 34 41 45 ns 6.0V 19 28 33 36 ns t PLH Maximum Propagation 2.0V 56 116 135 147 ns Delay Clear to Q 4.5V 25 36 42 46 ns 6.0V 20 29 34 37 ns t W Minimum Pulse Width 2.0V 57 123 144 157 ns A, B, Clear 4.5V 17 30 37 42 ns 6.0V 12 21 27 30 ns tREM Minimum Clear 2.0V 0 0 0 ns Removal Time 4.5V 0 0 0 ns 6.0V 0 0 0 ns tTLH , tTHL Maximum Output 2.0V 30 75 95 110 ns Rise and Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns tWQ(MIN) Minimum Output C EXT = 28 pF 2.0V 1.5 µs Pulse Width R EXT = 2 kΩ 4.5V 450 ns R EXT = 6 kΩ (VCC = 2V) 6.0V 380 ns R EXT = 10 kΩ Max 5.0V 1 1.1 1.14 1.15 ms C PD Power Dissipation 87 pF Capacitance (Note 5) C IN Maximum Input 12 20 20 20 pF Capacitance (Pins 7 & 15) C IN Maximum Input 6 10 10 10 pF Capacitance (other inputs)

5 www.fairchildsemi.com MM74HC221A Theory of Operation FIGURE 1. TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs, the monostable is in the quiescent state with the Q output LOW, and the timing capacitor C EXT com- pletely charged to VCC . When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC ) a valid trigger is recognized, which turns on comparator C1 and N-channel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor C EXT rap- idly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and tran- sistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor C EXT begins to charge through the timing resistor, REXT , toward VCC . When the voltage across CEXT equals VREF2 , comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to V CC (while input A is at GND and input clear is at VCC 2). The MM74HC221 can also be triggered when clear goes from GND to VCC (while A is at Gnd and B is at VCC 6). It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the MM74HC221 is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of C EXT , REXT , or the duty cycle of the input waveform. The MM74HC221 is non-retriggerable and will ignore input transitions on A and B until it has timed out 3 and 4. RESET OPERATION These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to V CC by turning on transistor Q1 5. When the voltage on the capacitor reaches VREF2 , the reset latch will clear and then be ready to accept another pulse. If the clear input is held LOW, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification.

www.fairchildsemi.com 6 MM74HC221A Typical Output Pulse Width vs. Timing Components Typical Distribution of Output Pulse Width, Part to Part Typical 1ms Pulse Width Variation vs. Supply Minimum R EXT vs. Supply Voltage Typical 1 ms Pulse Width Variation vs. Temperature Note: R and C are not subjected to temperature. The C is polypropylene.

7 www.fairchildsemi.com MM74HC221A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 8 MM74HC221A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC221A Dual Non-Retriggerable Monostable Multivibrator LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E