DM74LS193 FAIRCHILD | Alldatasheet

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■ Fully independent clear input ■ Synchronous operation ■ Cascading circuitry provided internally ■ Individual preset each flip-flop Ordering Code: Connection Diagram Order Number Package Number Package Description DM74LS193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 DM74LS193 Logic Diagram

3 www.fairchildsemi.com DM74LS193 Timing Diagram Note A: Clear overrides load, data, and count inputs Note B: When counting up, count-down input must be HIGH; when counting down, count-up input must be HIGH.

www.fairchildsemi.com 4 DM74LS193 Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Note 2: C L = 15 pF, RL = 2 kΩ , IA = 25°C and VCC = 5V. Note 3: C L = 50 pF, RL = 2 kΩ , IA = 25°C and VCC = 5V. Note 4: TA = 25°C and VCC = 5V. Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V. Operating Free Air Temperature Range −0°C to +70°C Supply Voltage 7V Input Voltage 7V Storage Temperature Range −65°C to +125°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 25 MHzClock Frequency (Note 3) tW Pulse Width of any Input (Note 4) 20 ns tSU Data Setup Time (Note 4) 20 ns tH Data Hold Time (Note 4) 0 ns tEN Enable Time to Clock (Note 4) 40 ns TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ Max Units (Note 5) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level Output V CC = Min, IOH = Max 2.5 3.4 V Voltage V IL = Max, VIH = Min 2.7 3.4 VOL LOW Level Output V CC = Min, IOL = Max 0.25 0.4 Voltage V IL = Max, VIH = Min 0.35 0.5 V IOL = 4m A ,VCC = Min 0.25 0.4 II Input Current @ Max Input Voltage V CC = Max, VI = 7V 0.1 mA IIH HIGH Level Input Current V CC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current V CC = Max, VI = 0.4V −0.4 mA IOS Short Circuit V CC = Max −20 −100 mA Output Current (Note 6) −20 −100 ICC Supply Current V CC = Max (Note 7) 19 34 mA

5 www.fairchildsemi.com DM74LS193 From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units M i nM a xM i nM a x fMAX Maximum Clock Frequency 25 20 MHz tPLH Propagation Delay Time Count Up 26 30 ns LOW-to-HIGH Level Output to Carry tPHL Propagation Delay Time Count Up 24 36 ns HIGH-to-LOW Level Output to Carry tPLH Propagation Delay Time Count Down 24 29 ns LOW-to-HIGH Level Output to Borrow tPHL Propagation Delay Time Count Down 24 32 ns HIGH-to-LOW Level Output to Borrow tPLH Propagation Delay Time Either Count 38 45 ns LOW-to-HIGH Level Output to Any Q tPHL Propagation Delay Time Either Count 47 54 ns HIGH-to-LOW Level Output to Any Q tPLH Propagation Delay Time Load to 40 41 ns LOW-to-HIGH Level Output Any Q tPHL Propagation Delay Time Load to 40 47 ns HIGH-to-LOW Level Output Any Q tPHL Propagation Delay Time Clear to 35 44 ns HIGH-to-LOW Level Output Any Q

www.fairchildsemi.com 6 DM74LS193 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0150” Narrow Body Package Number M16A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 7 www.fairchildsemi.com DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com