74191

DM74LS191 FAIRCHILD | Alldatasheet

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Technical content

Features

■ Counts binary ■ Single down/up count control line ■ Count enable control input ■ Ripple clock output for cascading ■ Asynchronously presettable with load control ■ Parallel outputs ■ Cascadable for n-bit applications ■ Average propagation delay 20 ns ■ Typical clock frequency 25 MHz ■ Typical power dissipation 100 mW Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description DM74LS191M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 DM74LS191 Connection Diagram Timing Diagram

3 www.fairchildsemi.com DM74LS191 Logic Diagram Pin (16) = VCC , Pin (8) = GND

www.fairchildsemi.com 4 DM74LS191 Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Note 2: TA = 25°C and VCC = 5V . Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all inputs grounded and all outputs open. Storage Temperature Range −65°C to +150°C Input Voltage 7V Operating Free Air Temp. Range 0 °C to +70°C Supply Voltage 7V Symbol Parameter Min Nom Max Units VCC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 20 MHz tW Pulse Width Clock 25 ns (Note 2) Load 35 tSU Data Setup Time (Note 2) 20 ns tH Data Hold Time (Note 2) 0 ns tEN Enable Time to Clock (Note 2) 30 ns TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ Max Units (Note 3) VI Input Clamp Voltage V CC = Min, II = − 18 mA −1.5 V VOH HIGH Level Output V CC = Min, IOH = Max Mil 2.5 3.4 Voltage V IL = Max, VIH = Min Com 2.7 3.4 V VOL LOW Level Output V CC = Min, IOL = Max 0.25 0.4 Voltage V IL = Max, VIH = Min 0.35 0.5 V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max Enable 0.3 mA Input Voltage V I = 7V Others 0.1 IIH HIGH Level Input V CC = Max Enable 60 µA Current V I = 2.7V Others 20 IIL LOW Level Input V CC = Max Enable −1.08 mA Current V I = 0.4V Others −0.4 IOS Short Circuit V CC = Max Mil −20 −100 mA Output Current (Note 4) Com −20 −100 ICC Supply Current V CC = Max (Note 5) 20 35 mA

5 www.fairchildsemi.com DM74LS191 From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units Min Max Min Max fMAX Maximum Clock 20 20 MHz Frequency tPLH Propagation Delay Time Load to 33 43 ns LOW-to-HIGH Level Output Any Q t PHL Propagation Delay Time Load to 50 59 ns HIGH-to-LOW Level Output Any Q tPLH Propagation Delay Time Data to 22 26 ns LOW-to-HIGH Level Output Any Q tPHL Propagation Delay Time Data to 50 62 ns HIGH-to-LOW Level Output Any Q t PLH Propagation Delay Time Clock to 20 24 ns LOW-to-HIGH Level Output Ripple Clock tPHL Propagation Delay Time Clock to 24 33 ns HIGH-to-LOW Level Output Ripple Clock tPLH Propagation Delay Time Clock to 24 29 ns LOW-to-HIGH Level Output Any Q t PHL Propagation Delay Time Clock to 36 45 ns HIGH-to-LOW Level Output Any Q tPLH Propagation Delay Time Clock to 42 47 ns LOW-to-HIGH Level Output Max/Min tPHL Propagation Delay Time Clock to 52 65 ns HIGH-to-LOW Level Output Max/Min t PLH Propagation Delay Time Up/Down to 45 50 ns LOW-to-HIGH Level Output Ripple Clock tPHL Propagation Delay Time Up/Down to 45 54 ns HIGH-to-LOW Level Output Ripple Clock tPLH Propagation Delay Time Down/Up to 33 36 ns LOW-to-HIGH Level Output Max/Min t PHL Propagation Delay Time Down/Up to 33 42 ns HIGH-to-LOW Level Output Max/Min tPLH Propagation Delay Time Enable to 33 36 ns LOW-to-HIGH Level Output Ripple Clock tPHL Propagation Delay Time Enable to 33 42 ns HIGH-to-LOW Level Output Ripple Clock

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS012, 0.150” Narrow Body Package Number M16A 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 300” Wide Package Number N16E